Simplified graded LDD transistor using controlled polysilicon gate profile

• US 6,274,443 B1
• Filed: 09/28/1998
• Issued: 08/14/2001
• Est. Priority Date: 09/28/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheung, Patrick K., Steffan, Paul J., Yu, Allen S.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/162,116
• Time in Patent Office: 1,051 Days
• Field of Search: 438/299, 438/210, 438/182, 438/286, 438/200, 438/199, 438/574, 438/579, 438/301, 438/303, 438/305, 438/306, 438/307, 438/595, 438/673, 438/701, 438/713, 438/978
• US Class Current: 438/299
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer

Abstract

An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.

Claims

1. A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer;

patterning and etching said first mask layer to form a first gate mask;

anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;

implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions and a doped resistor region in the semiconductor substrate;

anisotropically etching said first polysilicon gate to form a second polysilicon gate using said first gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;

removing said first gate mask;

forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;

selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;

anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate; and

removing said resistor protect mask to expose said resistor isolation.

2. The method as claimed in claim 1 wherein the step of implanting the semiconductor substrate with said dopant includes the step of penetrating portions of said sidewalls with said dopant to form said shallow extension junctions, said shallow extension junctions are graded junctions.

3. The method as claimed in claim 1 wherein the step of implanting the semiconductor substrate with said dopant forms deep junctions in a portion of the semiconductor substrate not shielded by said first polysilicon gate and adjacent said shallow extension junctions.

4. The method as claimed in claim 1 wherein the step of anisotropically etching said resistor protect layer includes over-etching said resistor protect layer to reduce the dimensions of said first sidewall spacer so that the top portion of said second polysilicon gate is exposed.

5. The method as claimed in claim 3 including the steps of:

forming a metallic layer over said doped resistor region, said second polysilicon gate, said first sidewall spacer, and said deep junctions after said step of removing said resistor protect mask to expose said resistor isolation; and

annealing the semiconductor substrate to form a metallic salicide on said doped resistor region not covered by said resistor isolation, the top portion of said second polysilicon gate, and portions of said deep junctions not shielded by said first sidewall spacer.

6. The method as claimed in claim 1 including the steps of:

forming a second mask layer over said first mask layer and patterning and etching said second mask layer to form a second gate mask prior to the step of patterning and etching said first mask layer to form said first gate mask; and

removing said second gate mask prior to the step of implanting the semiconductor substrate with said dopant.

7. The method as claimed in claim 1 wherein said first mask layer is a material selected from the group consisting of oxide and nitride.

8. A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer, wherein said first mask layer is a material selected from the group consisting of oxide and nitride;

forming a second mask layer over said first mask layer and patterning and etching said second mask layer to form a first gate mask;

patterning and etching said first mask layer to form a second gate mask;

anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;

implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions and a doped resistor region in the semiconductor substrate, wherein said dopant penetrates portions of said sidewalls to form said shallow extension junctions, said shallow extension junctions are graded junctions;

anisotropically etching said first polysilicon gate to form a second polysilicon gate using said second gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;

removing said second gate mask;

forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;

selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;

anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate; and

removing said resistor protect mask to expose said resistor isolation.

9. The method as claimed in claim 8 wherein the step of implanting the semiconductor substrate with said dopant forms deep junctions in a portion of the semiconductor substrate not shielded by said first polysilicon gate and adjacent said shallow extension junctions.

10. The method as claimed in claim 8 wherein the step of anisotropically etching said resistor protect layer includes over-etching said resistor protect layer to reduce the dimensions of said first sidewall spacer so that the top portion of said second polysilicon gate is exposed.

11. The method as claimed in claim 9 including the steps of:

forming a metallic layer over said doped resistor region, said second polysilicon gate, said first sidewall spacer, and said deep junctions after said step of removing said resistor protect mask to expose said resistor isolation; and

annealing the semiconductor substrate to form a metallic salicide on said doped resistor region not covered by said resistor isolation, the top portion of said second polysilicon gate, and portions of said deep junctions not shielded by said first sidewall spacer.

12. A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer, wherein said first mask layer is a material selected from the group consisting of oxide and nitride;

forming a second mask layer over said first mask layer and patterning and etching said second mask layer to form a first gate mask;

patterning and etching said first mask layer to form a second gate mask;

anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;

implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions, deep junctions in a portion of the semiconductor substrate not shielded by said first polysilicon gate and adjacent said shallow extension junctions, and a doped resistor region in the semiconductor substrate, wherein said dopant penetrates portions of said sidewalls to form said shallow extension junctions, said shallow extension junctions are graded junctions;

anisotropically etching said first polysilicon gate to form a second polysilicon gate using said second gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;

removing said second gate mask;

forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;

selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;

anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate, wherein the step of anisotropically etching said resistor protect layer includes the step of over-etching said resistor protect layer to reduce the dimensions of said first sidewall spacer so that the top portion of said second polysilicon gate is exposed; and

removing said resistor protect mask to expose said resistor isolation.

13. The method as claimed in claim 12 including the steps of:

forming a metallic layer over said doped resistor region, said second polysilicon gate, said first sidewall spacer, and said deep junctions after said step of removing said resistor protect mask to expose said resistor isolation; and

annealing the semiconductor substrate to form a metallic salicide on said doped resistor region not covered by said resistor isolation, the top portion of said second polysilicon gate, and portions of said deep junctions not shielded by said first sidewall spacer.