Specialized metal profile for via landing areas

• US 6,274,475 B1
• Filed: 08/02/2000
• Issued: 08/14/2001
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Shields, Jeffrey A.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/630,813
• Time in Patent Office: 377 Days
• Field of Search: 438/622, 438/625, 438/627, 438/629, 438/636, 438/652, 438/666, 438/669, 438/673, 438/688
• US Class Current: 438/622
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal feature, defined by gaps in a patterned metal layer, is formed with an inwardly tapering profile so that it is wider at the top than at the bottom. The metal feature advantageously presents a larger landing area for vias while maintaining the dimensions and intraline coupling capacitance required by design. The gaps in the patterned metal layer can be filled with a spin-on dielectric material such as spin-on glass (SOG) or hydrogen silsesquioxane (HSQ).

Claims

1. A method of manufacturing an interconnection structure in a semiconductor device, said method comprising:

forming a first dielectric layer on a substrate;

forming a patterned first metal layer having gaps on the first dielectric layer, wherein the patterned metal layer comprises a first metal feature having a top surface, a bottom surface, and side surfaces tapering inwardly from the top surface to the bottom surface;

forming second dielectric layer on the patterned first metal layer;

forming a through-hole in the second dielectric layer;

filling the through-hole with a second metal layer; and

forming a second metal feature on the second metal layer, said second metal feature being electrically connected to the first metal feature via the through-hole with the second metal layer.

2. A method of manufacturing a semiconductor device, said method comprising:

forming a first dielectric layer on a substrate;

forming a patterned metal layer having gaps on the first dielectric layer, wherein the patterned metal layer comprises a metal feature having a top surface, a bottom surface, and side surfaces tapering inwardly from the top surface to the bottom surface; and

forming second dielectric layer on the patterned metal layer, wherein the patterned metal layer is formed by;

depositing a lower metal layer;

depositing an intermediate layer of aluminum or an aluminum alloy;

depositing an upper anti-reflective coating;

etching to pattern the metal layer forming a plurality of gaps; and

filling the gaps with a dielectric material.

3. The method of claim 2, comprising controlling an amount of polymer formation during etching to control the slope of the inwardly tapering side surfaces.

4. The method of claim 3, comprising plasma etching the metal layer in the presence of an additive and controlling the amount of polymer formation by controlling the amount of the additive.

5. The method of claim 4, comprising etching with a Cl₂—

BCl₃ plasma containing at least one additive elected from the group consisting of N, CHF₃, CF₄, SF₆, and HCl.

6. The method of claim 5, comprising controlling the amount of polymer formation by reducing the amount of additive to about 5%-10% of the rate of flow.

7. The method of claim 2, wherein the side surfaces taper inwardly at a slope of about 80°

to about 89°

with respect to a line perpendicular to an upper surface of the first dielectric layer.

8. The method of claim 7, wherein the slope is about 85°

to about 88°

.

9. The method of claim 7, wherein the slope is about 81°

to about 86°

.

10. The method of claim 2, wherein the top surface has a width of about 0.54 μ

m to about 0.56 μ

m and the bottom surface has a width of about 0.44 μ

m to about 0.46 μ

m.

11. The method of claim 2, wherein the top surface has a width that exceeds a width of the bottom surface by at least 0.04 μ

m.

12. The method of claim 11, wherein the width of the top surface exceeds the width of the bottom surface by at least 0.08 μ

m.

13. The method of claim 2, wherein the bottom surface as a width of at least about 0.1 μ

m.

14. The method of claim 2, comprising filling the gaps with a spin-on glass (SOG).

15. The method of claim 2, comprising filling the gaps with hydrogen silsesquioxane (HSQ).

16. The method of claim 2, comprising:

etching to form a through-hole having an internal surface in the second dielectric layer and expose a portion of the top of the metal feature; and

depositing a layer of barrier material to line the internal surface of the through-hole.

17. The method of claim 16, comprising depositing the layer of barrier material by chemical vapor deposition.

18. The method of claim 16, comprising depositing the later of barrier material by sputtering.

19. The method of claim 16, wherein the lower metal layer comprises titanium or tungsten;

and the anti-reflective coating comprises titanium-titanium nitride.

20. The method of claim 19, comprising filling the through-hole with a conductive material to form a via.

21. The method of claim 20, wherein the conductive material comprises tungsten.

22. The method of claim 16, comprising forming a second patterned metal layer on the second dielectric layer, wherein the second patterned metal layer comprises a second metal feature electrically connected to the metal feature through the via.