Silicon multi-chip module packaging with integrated passive components and method of making

• US 6,274,937 B1
• Filed: 02/01/1999
• Issued: 08/14/2001
• Est. Priority Date: 02/01/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/241,061
• Time in Patent Office: 925 Days
• Field of Search: 257/698, 257/777, 257/778, 257/701, 257/723, 257/724, 257/528, 257/532
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0104 Zirconium [Zr]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An apparatus is provided for the supply of passive electronic components to a chip containing circuitry capable of operating in a communications system. The invention provides a silicon interposer element chip package which includes a silicon substrate and which is capable of carrying one or more IC chips and which does not suffer semiconductor leeching problems. A silicon substrate is formed from a silicon layer and an insulating layer, preferably an oxide. The invention also provides passive circuits within the interposer element oxide layer. The interposer element is then bonded to an integrated circuit chip using flip-chip processing.

Claims

1. A chip carrier comprising:

an interposer element comprising a semiconductor substrate layer and at least one insulating layer on a surface of said substrate layer, said insulating layer supporting at least one passive circuit element which is separated from said substrate layer by a portion of said insulating layer, said portion of said insulating layer having a thickness which is sufficient to electrically shield said at least one passive circuit element from said substrate layer.

2. The chip carrier of claim 1, further comprising at least one integrated circuit chip attached to said interposer element and electrically connected to said at least one passive circuit element.

3. The chip carrier of claim 2, wherein said semiconductor substrate layer comprises a silicon layer.

4. The chip carrier of claim 3, wherein said at least one insulating layer comprises an oxide layer.

5. The chip carrier of claim 4, wherein said oxide layer includes silicon dioxide (SiO₂).

6. The chip carrier of claim 5, wherein said oxide layer has a thickness within a range of three to five microns.

7. The chip carrier of claim 3, wherein said at least one insulating layer comprises a polyamide layer.

8. The chip carrier of claim 3, wherein said at least one passive element is embedded within said at least one insulating layer.

9. The chip carrier of claim 3, wherein said at least one passive element is formed on said at least one insulating layer.

10. The chip carrier of claim 3, further comprising a metallization pattern on or within said insulating layer connected with said at least one passive circuit device.

11. The chip carrier of claim 3, wherein said at least one insulating layer includes a plurality of passive circuit elements, said plurality of passive circuit elements separated from said substrate layer by a portion of said at least one insulating layer, said portion of said at least one insulating layer having a thickness such that said plurality of passive circuit elements are electrically shielded from the conductance of said substrate layer.

12. The chip carrier of claim 11, wherein said plurality of passive circuit elements includes a resistor element.

13. The chip carrier of claim 12, wherein said resistor element is a thin film metal resistor.

14. The chip carrier of claim 13, wherein said plurality of passive circuit elements includes a capacitor element.

15. The chip carrier of claim 14, wherein said capacitor element is a thin film capacitor.

16. The chip carrier of claim 15, wherein said thin film capacitor includes a dielectric layer.

17. The chip carrier of claim 16, wherein said dielectric layer is an oxide composition.

18. The chip carrier of claim 16, wherein said dielectric layer is an oxide-nitride-oxide composition.

19. The chip carrier of claim 15, wherein said plurality of passive circuit elements includes an inductor element.

20. The chip carrier of claim 19, wherein said inductor element is a spiral inductor.

21. The chip carrier of claim 20, wherein said plurality of passive circuit elements form at least one passive circuit device, said passive circuit device having at least one of said plurality of passive circuit elements and electrically connected to said at least one integrated circuit chip.

22. The chip carrier of claim 21, wherein said plurality of passive circuit elements form at least one passive circuit device used in radio frequency (RF) communications systems.

23. The chip carrier of claim 22, wherein said interposer element and said at least one integrated circuit are arranged to form circuitry used in RF communications systems.

24. The chip carrier of claim 23, wherein said at least one passive circuit device comprises a load amplifier.

25. The chip carrier of claim 23, wherein said at least one passive circuit device comprises a broad band amplifier.

26. The chip carrier of claim 23, wherein said at least one passive circuit device comprises an oscillator.

27. The chip carrier of claim 26, wherein said oscillator is a voltage controlled oscillator.

28. The chip carrier of claim 23, wherein said at least one integrated circuit chip comprises a chip having at least one logic device electrically connected to said interposer element.

29. The chip carrier of claim 28, wherein said chip contains analog circuitry.

30. The chip carrier of claim 28, wherein said at least one logic device is a transistor.

31. The chip carrier of claim 30, wherein said chip contains digital circuitry.

32. The chip carrier of claim 31, wherein said chip is a microprocessor.

33. The chip carrier of claim 31, wherein said chip is a memory chip.

34. The chip carrier of claim 29, wherein said at least one integrated circuit chip is attached to said interposer element by solder joints.

35. The chip carrier of claim 34, wherein said at least one integrated circuit chip is attached to said interposer element through flip-chip bonding.

36. The chip carrier of claim 35, wherein said solder joints have varying compositions such that each of said solder joints has a selective melting temperature.

37. The chip carrier of claim 29, wherein said at least one integrated circuit chip is attached to said interposer element by a conductive adhesive substance.

38. The chip carrier of claim 29, wherein a bonding agent is located in the area between the said at least one integrated circuit chip and said insulating layer.

39. The chip carrier of claim 38, wherein said bonding agent is epoxy.

40. The chip carrier of claim 29, wherein said chip carrier is encapsulated to form a circuit package, said circuit package having conducting leads on an outer side of said package.

41. The chip carrier of claim 40, further comprising conductive leads connecting the chip carrier to said conductive package leads of said circuit package.

42. The chip carrier of claim 2, wherein said interposer element includes first and second insulating layers on opposing surfaces of said substrate.

43. The chip carrier of claim 42, wherein each of said first and second insulating layers has at least one passive circuit element separated from said substrate layer by a portion of said first and second insulating layers having a thickness such that each of said at least one passive circuit elements is electrically shielded from the conductance of said substrate layer.

44. The chip carrier of claim 43 wherein said first and second insulating layers include a plurality of passive circuit elements.

45. The chip carrier of claim 44, wherein at least one of said first and second insulating layers has at least one active circuit element.

46. The chip carrier of claim 1, wherein said substrate layer is comprised of gallium-arsenide.

47. The chip carrier of claim 46, wherein said insulating layer is comprised of gallium-arsenide-oxide.

48. A chip carrier comprising:

an interposer element comprising a semiconductor substrate layer and at least one insulating layer on a surface of said substrate layer, said insulating layer supporting at least one passive circuit element which is separated from said substrate layer by a portion of said insulating layer, said portion of said insulating layer having a thickness which is sufficient to electrically shield said at least one passive circuit element from said substrate layer;

at least one integrated circuit chip attached to said interposer element and electrically connected to said at least one passive circuit element; and

said interposer element and said at least one integrated circuit contain electrical elements which form circuitry for use in radio frequency (RF) communications systems.

49. The chip carrier of claim 48, wherein at least one of said plurality of insulating layers comprises an oxide layer.

50. The chip carrier of claim 49, wherein said oxide layer includes silicon dioxide (SiO₂).

51. The chip carrier of claim 50, wherein said oxide layer has a thickness within a range of three to five microns.

52. The chip carrier of claim 48, wherein at least one of said plurality of insulating layers comprises a polyamide layer.

53. The chip carrier of claim 48, wherein at least one of said plurality of passive elements is embedded within said at least one insulating layer.

54. The chip carrier of claim 48, wherein at least one of said plurality of passive elements is formed on said at least one insulating layer.

55. The chip carrier of claim 48, further comprising a metallization pattern on or within said insulating layer connected with said at least one passive circuit device.

56. The chip carrier of claim 55, wherein said plurality of passive circuit elements includes a resistor element.

57. The chip carrier of claim 56, wherein said resistor element is a thin film metal resistor.

58. The chip carrier of claim 57, wherein said plurality of passive circuit elements includes a capacitor element.

59. The chip carrier of claim 58, wherein said capacitor element is a thin film capacitor.

60. The chip carrier of claim 59, wherein said thin film capacitor includes a dielectric layer.

61. The chip carrier of claim 60, wherein said dielectric layer is an oxide composition.

62. The chip carrier of claim 60, wherein said dielectric layer is an oxide-nitride-oxide composition.

63. The chip carrier of claim 60, wherein said plurality of passive circuit elements includes an inductor element.

64. The chip carrier of claim 63, wherein said inductor element is a spiral inductor.

65. The chip carrier of claim 64, wherein said plurality of passive circuit elements form at least one passive circuit device, said passive circuit device having at least one of said plurality of passive circuit elements and electrically connected to said at least one integrated circuit chip.

66. The chip carrier of claim 65, wherein said plurality of passive circuit elements form at least one passive circuit device used in radio frequency (RF) communications systems.

67. The chip carrier of claim 66, wherein said at least one passive circuit device comprises a load amplifier.

68. The chip carrier of claim 66, wherein said at least one passive circuit device comprises a broad band amplifier.

69. The chip carrier of claim 66, wherein said at least one passive circuit device comprises an oscillator.

70. The chip carrier of claim 69, wherein said oscillator is a voltage controlled oscillator.

71. The chip carrier of claim 66, wherein said at least one integrated circuit chip comprises a chip having at least one logic device electrically connected to said interposer element.

72. The chip carrier of claim 71, wherein said chip contains analog circuitry.

73. The chip carrier of claim 71, wherein said at least one logic device is a transistor.

74. The chip carrier of claim 73, wherein said chip contains digital circuitry.

75. The chip carrier of claim 74, wherein said chip is a microprocessor.

76. The chip carrier of claim 74, wherein said chip is a memory chip.

77. The chip carrier of claim 71, wherein said at least one integrated circuit chip is attached to said interposer element by solder joints.

78. The chip carrier of claim 77, wherein said at least one integrated circuit chip is attached to said interposer element through flip-chip bonding.

79. The chip carrier of claim 78, wherein said solder joints have varying compositions such that each of said solder joints has a selective melting temperature.

80. The chip carrier of claim 71, wherein said at least one integrated circuit chip is attached to said interposer element by a conductive adhesive substance.

81. The chip carrier of claim 71, wherein a bonding agent is located in the area between the said at least one integrated circuit chip and said insulating layer.

82. The chip carrier of claim 81, wherein said bonding agent is epoxy.

83. The chip carrier of claim 71, wherein said chip carrier is encapsulated to form a circuit package, said circuit package having conducting leads on an outer side of said package.

84. The chip carrier of claim 83, further comprising conductive leads connecting the chip carrier to said conductive package leads of said circuit package.

85. The chip carrier of claim 71, wherein said interposer element includes first and second insulating layers on opposing surfaces of said silicon substrate.

86. The chip carrier of claim 85, wherein each of said first and second insulating layers has a plurality of passive circuit elements separated from said silicon substrate layer by a portion of said first and second insulating layers having a thickness such that said plurality of passive circuit elements are electrically shielded from the conductance of said silicon substrate layer.

87. The chip carrier of claim 86, wherein at least one of said first and second insulating layers has at least one active circuit element.