Segmented architecture for wafer test and burn-in

• US 6,275,051 B1
• Filed: 01/29/1999
• Issued: 08/14/2001
• Est. Priority Date: 12/29/1997
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Nihon Micronics
• Original Assignee: International Business Machines Corporation
• Inventors: Barringer, Dennis R., Conti, Dennis R., Laforce, Mark R., Crafts, James M., Bachelder, Thomas W., Schmidt, Roger R., Gardell, David L., White, Wade H., Perry, Charles H., Gaschke, Paul M., Van Horn, Joseph J.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US09/240,121
• Time in Patent Office: 928 Days
• Field of Search: 324/754, 324/757, 324/758, 324/760, 324/765
• US Class Current: 324/754.03
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04

Abstract

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

Claims

1. A test head, comprising:

a first board and a second board;

said first board having a probe side and a connection side, said probe side having probes for contacting at least one die on a product wafer, said connection side being adapted for electrical connections to said second board; and

said second board having a contact side and a tester chip side, said contact side having contacts for electrical connection to said connection side of said first board, said tester chip side having a tester chip for distributing power to said die or for testing said die.

2. The test head as recited in claim 1, wherein said probes are for contacting substantially all the dies on the wafer.

3. The apparatus as recited in claim 1, wherein said first board comprises a material having a thermal coefficient of expansion matching that of the product wafer.

4. The apparatus as recited in claim 3, wherein said material comprises one of glass ceramic, aluminum nitride, Kovar, Invar, tungsten, and molybdenum.

5. The apparatus as recited in claim 1, wherein said second board comprises a material having a thermal coefficient of expansion matching that of the product wafer.

6. The test head as recited in claim 1, wherein said second board has a plurality of said tester chips.

7. The test head as recited in claim 1, wherein said first board comprises a material having a thermal coefficient of expansion matching that of the product wafer, said first board comprises a base and a thin film layer for personalizing said first board for contacting the die, said base being generic, said first board being tiled, all individual tiles of said first board being identical, said test head further comprising an interposer between said first board and said second board, said interposer comprising a housing mounted in a frame.

8. The test head as recited in claim 1, further comprising thermal resistance between said first and second board.

9. The test head as recited in claim 8, wherein said thermal resistance comprises a space between said first and second board, air providing said thermal resistance.

10. The test head as recited in claim 8, wherein said thermal resistance comprises a thermally resistant material between said first and second board.

11. The test head as recited in claim 10, wherein said thermally resistant material comprises an interposer between said first and second board.

12. The test head as recited in claim 8, wherein said thermal resistance comprises air or vacuum between said first and second board.

13. The test head as recited in claim 1, wherein said first board comprised a base and a thin film layer for personalizing said first board for contacting the die.

14. The test head as recited in claim 13, wherein said thin film layer comprises a plurality of conductive and insulating layers.

15. The test head as recited in claim 13, wherein said base is generic, personalization of said first board being exclusively in said thin film layer.

16. The test head as recited in claim 1, wherein said first board is tiled.

17. The test head as recited in claim 16, wherein all individual tiles of said first board are identical.

18. The test head as recited in claim 17, wherein said individual tiles are rotated with respect to each other.

19. The test head as recited in claim 1, further comprising a decoupling capacitor between side first board and said second board.

20. The test head as recited in claim 19, there being a plurality of power pads on said first board, wherein said decoupling capacitor is provided on each said power pad.

21. The test head as recited in claim 1, wherein said second board is usable for testing a family of product wafers.

22. The test head as recited in claim 1, wherein power from the power supply is distributed to said at least on tester chip through said second board.

23. The test head as recited in claim 1, wherein said tester chip comprises means for disconnecting contact to the power pads of a product chip.

24. The test as recited in claim 1, wherein said second board further comprises a plurality of contacts for connecting said test head to a tester.

25. The test head as recited in claim 1, further comprising an interposer between said first board and said second board.

26. The test head as recited in claim 25 wherein said interposer comprises housings mounted in a frame.

27. The test head as recited in claim 26 wherein housings comprise plastic, and said frame is thermally matched to said personalization board.