Semiconductor integrated circuit

• US 6,275,055 B1
• Filed: 04/06/1999
• Issued: 08/14/2001
• Est. Priority Date: 12/01/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Asahina, Katsushi, Hyozo, Masahiko
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US09/286,291
• Time in Patent Office: 861 Days
• Field of Search: 324/755, 324/765, 324/754, 324/158.1, 324/73.1, 324/763, 714/727, 714/728, 371/22.5, 371/12.5, 371/22.4
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test

Abstract

A semiconductor integrated circuit, in which an input buffer, an output buffer, and an input/output buffer connected to signal pins respectively each as an object for a DC test are connected to a single DC test pin through discretely provided switches, all the switches are OFF in an ordinary state, and when the DC test is to be performed, the switches are successively turned ON one by one in a state where the DC test pin is connected to an LSI tester. With the operation, various types of DC test such as a pin contest, an input leak test and an output voltage test can be performed by using a LSI tester having a smaller number of pins than a number of pins in an LSI without requiring a connection such that the signal pins as objects for the test are in one-to-one correspondence with the pin electronics in the LSI tester.

Claims

1. A semiconductor integrated circuit comprising:

a plurality of signal pins each for executing signal transaction to the outside;

at least one signal pin designated for a DC test, when a DC test among a) a test for checking connection between the signal pins and an external connected tester, b) a test for checking a current leak failure to the signal pins provided for signal input from the outside, and c) a test for checking a voltage level output from the signal pins provided for signal output to the outside is executed, said at least one signal pin connected to the external tester;

a plurality of internal circuits connected to the plurality of signal pins respectively and provided for signal transactions to the outside; and

a plurality of switches, each connected between said at least one signal pin designated for the DC test and a signal path between each of the plurality of internal circuits and the respective remaining signal pin, said plurality of switches for successively connecting the plurality of internal circuits to the at least one signal pin designated for the DC test and said plurality of switches being conductive one by one successively when the DC test is performed.

2. A semiconductor integrated circuit according to claim 1;

wherein said internal circuit comprises protection diodes and a buffer circuit for input or output of a signal.

3. A semiconductor integrated circuit according to claim 2;

wherein said switch comprises a transfer gate.

4. A semiconductor integrated circuit according to claim 1 incorporating a circuit for generating signals for successively turning ON said switches;

wherein this circuit comprises a shift register for shifting signals to turn ON said switches and successively outputting the signals to the switches respectively.

5. A semiconductor integrated circuit according to claim 3;

wherein parasitic diodes are formed at said transfer gate, and an N-channel transistor for cutting off a current path with the parasitic diodes on DC testing is provided between said parasitic diodes and a power unit.

6. A semiconductor integrated circuit comprising:

a plurality of first signal pins each for executing signal transaction to the outside of said semiconductor integrated circuit;

a plurality of signal lines connected to said plurality of first signal pins respectively;

a plurality of internal circuits connected to said plurality of signal lines respectively, each internal circuit including at least one of an input buffer receiving a signal from the corresponding signal line and an output buffer providing a signal for the corresponding signal line;

a second signal pin, and

a plurality of switches connecting and disconnecting said second signal pin to said plurality of said signal lines respectively.

7. The semiconductor integrated circuit of claim 6, further comprising:

a third signal pin receiving a control signal, and a control circuit connected to said third signal pin, for controlling to turn on and off said plurality of switches on the basis of the control signal.

8. The semiconductor integrated circuit of claim 7, wherein said control circuit including a plurality of flip-flops having outputs connected to said plurality of switches respectively, said plurality of flip-flops forming a shift register.

9. The semiconductor integrated circuit of claim 8, wherein said shift register shifting the control signal receiving from said third signal pin.

10. The semiconductor integrated circuit of claim 7, wherein said control circuit renders said plurality of switches conductive successively the basis of the control signal.

11. The semiconductor integrated circuit of claim 6, said second signal pin is connected to a tester device when a DC test is executed.

12. The semiconductor integrated circuit of claim 6, further comprising:

a plurality of first diodes connected between a first power supply line and said plurality of signal lines, respectively, and

a plurality of second diodes connected between a second power supply line and said plurality of signal lines, respectively.

13. The semiconductor integrated circuit of claim 6, further comprising:

a plurality of first diodes each connected between a first power supply line and said second signal pin, and

a plurality of second diodes each connected between a second power supply line and said second signal pin.

14. The semiconductor integrated circuit of claim 13, further comprising:

a plurality of transistors provided correspondingly to said plurality of switches, each transistor for cutting off a current path on one of said plurality of first diodes and being conductive simultaneously with the corresponding switch.