Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits

• US 6,275,064 B1
• Filed: 12/22/1997
• Issued: 08/14/2001
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantis Corp (Lattice Semiconductor Corporation)
• Inventors: Agrawal, Om P., Sharpe-Geisler, Bradley A., Chang, Herman M., Tran, Giap H.
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/996,361
• Time in Patent Office: 1,331 Days
• Field of Search: 326/37, 326/38, 326/39, 326/40, 326/41, 326/47, 365/230
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17792 for operating speed
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A Field Programmable Gate Array (FPGA) device includes a plurality of variable grain blocks (VGBs) and a plurality of interconnect lines for providing program-defined routing of signals between the VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. Each CBB includes 6 term inputs, 2 control inputs and one direct connect output. Each CBB includes two configurable building elements having 3 term inputs and 1 control input, respectively. The plurality of interconnect lines includes a direct connect architecture for providing programmably-selectable, dedicated connections between a center VGB, in particular a CBB, and neighboring VGBs. The direct connect architecture and positioning of inputs and outputs enables 1) enhanced flexibility and efficiency in the configuration placement and routing software 2) efficiently emulates random logic nets and 3) reduces many direct connect line wire lengths.

Claims

1. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBS) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein first and second inputs are located at the top side;

(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the second VGB directly to a respective input of the first VGB; and

(b.2) a second direct connect line connecting the second output of the second VGB directly to respective input of the first VGB.

2. The field programmable gate array device of claim 1, further including:

(a.3) a third VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

wherein the second portion includes;

(b.3) a third direct connect line connecting the first output of the third VGB directly to a respective input of the first VGB; and

(b.4) a fourth direct connect line connecting the second output of the third VGB directly to a respective input of the first VGB.

3. The field programmable gate array device of claim 2, further including:

(a.4) a fourth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the bottom side;

(a.5) a fifth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the top side;

wherein the second portion includes;

(b.5) a fifth direct connect line connecting the first output of the fourth VGB directly to a respective input of the first VGB; and

(b.6) a sixth direct connect line connecting the second output of the fourth VGB directly to a respective input of the first VGB;

(b.7) a seventh direct connect line connecting the first output of the fifth VGB directly to a respective input of the first VGB; and

(b.8) an eighth direct connect line connecting the second output of the fifth VGB directly to a respective input of the first VGB.

4. The field programmable gate array device of claim 3, further including:

(a.6) a sixth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the top side;

(a.7) a seventh VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the top side;

wherein the second portion includes;

(b.9) a ninth direct connect line connecting a first output of the sixth VGB directly to a respective input of the first VGB; and

(b.10) a tenth direct connect line connecting the second output of the sixth VGB directly to a respective input of the first VGB;

(b.11) an eleventh direct connect line connecting the first output of the seventh VGB directly to a respective input of the first VGB; and

(b.12) a twelfth direct connect line connecting the second output of the seventh VGB directly to a respective input of the first VGB.

5. The field programmable gate array device of claim 4, further including:

(a.8) an eighth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the top side; and

(a.9) a ninth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the bottom side;

wherein the second portion includes;

(b.13) a thirteenth direct connect line connecting the first output of the eighth VGB directly to a respective input of the first VGB; and

(b.14) a fourteenth direct connect line connecting the second output of the eighth VGB directly to a respective input of the first VGB;

(b.15) a fifteenth direct connect line connecting the first output of the ninth VGB directly to a respective input of the first VGB; and

(b.16) a sixteenth direct connect line connecting the second output of the ninth VGB directly to a respective input of the first VGB.

6. The field programmable gate array device of claim 5, wherein the eighth VGB includes a first and a second CBB having the first and the second respective outputs.

7. The field programmable gate array device of claim 4, wherein the sixth VGB includes a first and a second CBB having the first and the second respective outputs.

8. The field programmable gate array device of claim 3, wherein the fourth VGB includes a first and a second CBB having the first and the second respective outputs.

9. The field programmable gate array device of claim 2, wherein the third VGB includes a first and a second CBB having the first and the second respective outputs.

10. The field programmable partitionable gate array device of claim 1, wherein the first VGB includes a first configurable building block (“

CBB”

) having a first and a second input and the second VGB includes a first and a second CBB having the first and the second respective outputs.

11. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBS includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the top side;

(a.2) a first adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

(a.3) a second adjacent VGB having a top right, bottom and left side, wherein first and second outputs are located at the bottom side;

(a.4) a third adjacent VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the top side;

(a.5) a fourth adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the bottom side;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first adjacent VGB directly to a respective input of the first VGB; and

(b.2) a second direct connect line connecting the second output of the first adjacent VGB directly to a respective input of the first VGB;

(b.3) a third direct connect line connecting the first output of the second adjacent VGB directly to a respective input of the first VGB;

(b.4) a fourth direct connect line connecting the second output of the second adjacent VGB directly to a respective input of the first VGB;

(b.5) a fifth direct connect line connecting the first output of the third adjacent VGB directly to a respective input of the first VGB;

(b.6) a sixth direct connect line connecting the second output of the third adjacent VGB directly to a respective input of the first VGB;

(b.7) a seventh direct connect line connecting the first output of the fourth adjacent VGB directly to a respective input of the first VGB; and

(b.8) an eighth direct connect line connecting the second output of the fourth adjacent VGB directly to a respective input of the first VGB.

12. A field programable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the top side;

(a.2) a first next-adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

(a.3) a second next-adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

(a.4) a third next-adjacent VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the top side;

(a.5) a fourth next-adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first next-adjacent VGB directly to a respective input of the first VGB; and

(b.2) a second direct connect line connecting the second output of the first next-adjacent VGB directly to a respective input of the first VGB;

(b.3) a third direct connect line connecting the first output of the second next-adjacent VGB directly to a respective input of the first VGB;

(b.4) a fourth direct connect line connecting the second output of the second next-adjacent VGB directly to a respective input of the first VGB;

(b.5) a fifth direct connect line connecting the first output of the third next-adjacent VGB directly to a respective input of the first VGB;

(b.6) a sixth direct connect line connecting the second output of the third next-adjacent VGB directly to a respective input of the first VGB;

(b.7) a seventh direct connect line connecting the first output of the fourth next-adjacent VGB directly to a respective input of the first VGB; and

(b.8) an eighth direct connect line connecting the second output of the fourth next-adjacent VGB directly to a respective input of the first VGB.

13. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein said plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

(a.3) a third VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the top side;

(a.4) a fourth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

(a.5) a fifth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

wherein the first, second, third, fourth and fifth VGBs are arranged consecutively in a row;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first VGB directly to a respective input of the third VGB;

(b.2) a second direct connect line connecting the second output of the first VGB directly to a respective input of the third VGB;

(b.3) a third direct connect line connecting the first output of the second VGB directly to a respective input of the third VGB;

(b.4) a fourth direct connect line connecting the second output of the second VGB directly to a respective input of the third VGB;

(b.5) a fifth direct connect line connecting the first output of the fourth VGB directly to a respective input of the third VGB;

(b.6) a sixth direct connect line connecting the second output of the fourth VGB directly to a respective input of the third VGB;

(b.7) a seventh direct connect line connecting the first output of the fifth VGB directly to a respective input of the third VGB; and

(b.8) an eighth direct connect line connecting the second output of the fifth VGB directly to a respective function input of the third VGB.

14. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein said plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a first and second outputs are located at the top side;

(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the bottom side;

(a.3) a third VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the top side;

(a.4) a fourth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the bottom side;

(a.5) a fifth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the top side;

wherein the first, second, third, fourth and fifth VGBs are arranged consecutively in a column;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first VGB directly to a respective input of the third VGB;

(b.2) a second direct connect line connecting the second output of the first VGB directly to a respective input of the first VGB;

(b.3) a third direct connect line connecting the first output of the second VGB directly to a corresponding input of the third VGB;

(b.4) a fourth direct connect line connecting the second output of the second VGB directly to a respective input of the third VGB;

(b.5) a fifth direct connect line connecting the first output of the fourth VGB directly to a respective input of the third VGB;

(b.6) a sixth direct connect line connecting the second output of the fourth VGB directly to a respective input of the third VGB;

(b.7) a seventh direct connect line connecting the first output of the fifth VGB directly to a respective input of the third VGB; and

(b.8) an eighth direct connect line connecting the second output of the fifth VGB directly to a corresponding input of the third VGB.

15. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the left side;

(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the right side;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the second VGB directly to a respective input of the first VGB; and

(b.2) a second direct connect line connecting the second output of the second VGB directly to a respective input of the first VGB.

16. The field programmable gate array device of claim 15, further including:

(a.3) a third VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

wherein the second portion includes;

(b.3) a third direct connect line connecting the first output of the third VGB directly to a respective input of the first VGB; and

(b.4) a fourth direct connect line connecting the second output of the third VGB directly to a respective input of the first VGB.

17. The field programmable gate array device of claim 16, further including:

(a.4) a fourth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

(a.5) a fifth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the left side;

wherein said second portion includes;

(b.5) a fifth direct connect line connecting the first output of the fourth VGB directly to a respective input of the first VGB;

(b.6) a sixth direct connect line connecting the second output of the fourth VGB directly to a corresponding input of the first VGB;

(b.7) a seventh direct connect line connecting the first output of the fifth VGB directly to a respective input of the first VGB; and

(b.8) an eighth direct connect line connecting the second output of the fifth VGB directly to a corresponding function input of the first VGB.

18. The field programmable gate array device of claim 17 further including:

(a.6) a sixth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the right side;

(a.7) a seventh VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the left side;

wherein the second portion includes;

(b.9) a ninth direct connect line connecting the first output of the sixth VGB directly to a respective input of the first VGB; and

(b.10) a tenth direct connect line connecting the second output of the sixth VGB directly to a respective input of the first VGB;

(b.11) an eleventh direct connect line connecting the first output of the seventh VGB directly to a respective input of the first VGB; and

(b.12) a twelfth direct connect line connecting the second output of the seventh VGB directly to a respective input of the first VGB.

19. The field programmable gate array device of claim 18, further including:

(a.8) an eighth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the left side; and

(a.9) a ninth VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the left side;

wherein the second portion includes;

(b.13) a thirteenth direct connect line connecting the first output of the eighth VGB directly to a respective input of the first VGB; and

(b.14) a fourteenth direct connect line connecting the second output of the eighth VGB directly to a respective input of the first VGB;

(b.15) a fifteenth direct connect line connecting a first output of the ninth VGB directly to a respective input of the first VGB; and

(b.16) a sixteenth direct connect line connecting the second output of the ninth VGB directly to a respective input of the first VGB.

20. The field programmable gate array device of claim 19, wherein the eighth VGB includes a first and second CBB having the first and second respective outputs.

21. The field programmable gate array device of claim 18, wherein the sixth VGB includes a first and second CBB having the first and second respective outputs.

22. The field programmable gate array device of claim 17, wherein the fourth VGB includes a first and second CBB having the first and second respective outputs.

23. The field programmable gate array device of claim 16, wherein the third VGB includes a first and second CBB having the first and second respective outputs.

24. The field programmable gate array device of claim 15, wherein the first VGB includes a first CBB having a first and second input and the second VGB includes a first and second CBB having the first and second respective outputs.

25. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the left side;

(a.2) a first adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the right side;

(a.3) a second adjacent VGB having a top right, bottom and left side, wherein first and second outputs are located at the left side;

(a.4) a third adjacent VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the right side;

(a.5) a fourth adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first adjacent VGB directly to a respective input of the first VGB; and

(b.2) a second direct connect line connecting the second output of the first adjacent VGB directly to a respective input of the first VGB;

(b.3) a third direct connect line connecting the first output of the second adjacent VGB directly to a respective input of the first VGB;

(b.4) a fourth direct connect line connecting the second output of the second adjacent VGB directly to a respective input of the first VGB;

(b.5) a fifth direct connect line connecting the first output of the third adjacent VGB directly to a respective input of the first VGB;

(b.6) a sixth direct connect line connecting the second output of the third adjacent VGB directly to a respective input of the first VGB;

(b.7) a seventh direct connect line connecting the first output of the fourth adjacent VGB directly to a respective input of the first VGB; and

(b.8) an eighth direct connect line connecting the second output of the fourth adjacent VGB directly to a respective input of the first VGB.

26. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the left side;

(a.2) a first next-adjacent VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

(a.3) a second next-adjacent VGB having a top right, bottom and left side, wherein first and second outputs are located at the left side;

(a.4) a third next-adjacent VGB having a top, right, bottom, and left side, wherein first and second outputs are located at the left side;

(a.5) a fourth next-adjacent VGB having a top right bottom and left side, wherein first and second outputs are located at the left side;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first next-adjacent VGB directly to a respective input of the first VGB; and

(b.2) a second direct connect line connecting the second output of the first next-adjacent VGB directly to a respective input of the first VGB;

(b.3) a third direct connect line connecting the first output of the second next-adjacent VGB directly to a respective input of the first VGB;

(b.4) a fourth direct connect line connecting the second output of the second next-adjacent VGB directly to a respective input of the first VGB;

(b.5) a fifth direct connect line connecting the first output of the third next-adjacent VGB directly to a respective input of the first VGB;

(b.6) a sixth direct connect line connecting the second output of the third next-adjacent VGB directly to a respective input of the first VGB;

(b.7) a seventh direct connect line connecting the first output of the fourth next-adjacent VGB directly to a respective input of the first VGB; and

(b.8) an eighth direct connect line connecting the second output of the fourth next-adjacent VGB directly to a respective input of the first VGB.

27. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBs) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the right side;

(a.3) a third VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the left side;

(a.4) a fourth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the right side;

(a.5) a fifth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

wherein the first, second, third, fourth and fifth VGBs are arranged consecutively in a row;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first VGB directly to a respective input of the third VGB;

(b.2) a second direct connect line connecting the second output of the first VGB directly to a respective input of the third VGB;

(b.3) a third direct connect line connecting the first output of the second VGB directly to a respective input of the third VGB;

(b.4) a fourth direct connect line connecting the second output of the second VGB directly to a respective input of the third VGB;

(b.5) a fifth direct connect line connecting the first output of the fourth VGB directly to a respective input of the third VGB;

(b.6) a sixth direct connect line connecting the second output of the fourth VGB directly to a respective input of the third VGB;

(b.7) a seventh direct connect line connecting the first output of the fifth VGB directly to a respective input of the third VGB; and

(b.8) an eighth direct connect line connecting the second output of the fifth VGB directly to a respective input of the third VGB.

28. A field programmable gate array device comprising:

(a) a plurality of variable grain blocks (VGBS) each carrying out one or more program-defined logic functions, each having inputs for receiving respective input signals and each having outputs for outputting respective output signals; and

(b) a plurality of interconnect lines for routing signals between the plurality of variable grain blocks (VGBs), the plurality of interconnect lines including a programmably configurable first portion for providing program-defined routing of signals between the plurality of variable grain blocks (VGBs);

wherein the plurality of VGBs includes;

(a.1) a first VGB having a top, right, bottom and left side, wherein a first and second outputs are located at the left side;

(a.2) a second VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

(a.3) a third VGB having a top, right, bottom and left side, wherein a plurality of inputs are located at the left side;

(a.4) a fourth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

(a.5) a fifth VGB having a top, right, bottom and left side, wherein first and second outputs are located at the left side;

wherein the first, second, third, fourth and fifth VGBs are arranged consecutively in a column;

wherein the plurality of interconnect lines further includes a second portion comprising;

(b.1) a first direct connect line connecting the first output of the first VGB directly to a respective input of the third VGB;

(b.2) a second direct connect line connecting the second output of the first VGB directly to a respective input of the first VGB;

(b.3) a third direct connect line connecting the first output of the second VGB directly to a respective input of the third VGB;

(b.4) a fourth direct connect line connecting the second output of the second VGB directly to a respective input of the third VGB;

(b.5) a fifth direct connect line connecting the first output of the fourth VGB directly to a respective input of the third VGB;

(b.6) a sixth direct connect line connecting the second output of the fourth VGB directly to a respective input of the third VGB;

(b.7) a seventh direct connect line connecting the first output of the fifth VGB directly to a respective input of the third VGB; and

(b.8) an eighth direct connect line connecting the second output of the fifth VGB directly to a respective input of the third VGB.