Clock signal control circuit and method and synchronous delay circuit

• US 6,275,091 B1
• Filed: 07/20/2000
• Issued: 08/14/2001
• Est. Priority Date: 07/23/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Saeki, Takanori
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/620,378
• Time in Patent Office: 390 Days
• Field of Search: 327/141, 327/144, 327/153, 327/161, 327/264, 327/266, 327/276, 327/277, 327/278, 327/280, 327/281, 327/284, 327/285, 327/287, 327/288, 327/392, 327/396, 327/399-401
• US Class Current: 327/396
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A clock signal control circuit that permits the on-chip circuit dimensional size to be reduced is provided. The clock signal control circuit includes a plurality of amplifier circuit elements amplifying the input clock signal and a plurality of switching elements switching the passage of the clock signal on and off, wherein the plurality of amplifier circuit elements and the plurality of switching elements are connected in such a way that the amplifier circuit elements may be connected in a series fashion when they are operational. Selecting those switching elements that are switched on causes the amplifier circuit elements to be switched so that their series-fashion connection can be reversed to allow the clock signal to travel in the backward direction.

Claims

1. A clock signal control method for a delay circuit, comprising the steps of:

providing a delay circuit comprising a plurality of amplifier circuit elements each amplifying a clock signal applied thereto; and

a plurality of switching elements each switching passage of the clock signal on and off,

connecting said plurality of amplifier circuit elements in a series fashion through said switching elements that are switched on; and

selecting said switching elements that are switched on, thereby allowing a direction in which the clock signal is traveling through said plurality of amplifier circuit elements connected in a series fashion to be switched between a forward direction and a backward direction.

2. The method as defined in claim 1, wherein said switching elements are disposed in parallel two lines with said amplifier circuit elements intervening between said two lines, and wherein any of said forward and backward directions is selected by selectively establishing a meander-like path of the series fashion.

3. The method as defined in claim 1, wherein one of the two directions is established by connecting adjacent two of said amplifier circuit elements via one of said switching elements selected to be ON to form one meander-like path, while the other of the two direction is established by connecting said adjacent two amplifier circuit elements via another one of said switching elements selected to be ON disposed opposing to said one of said switching elements now selected to be OFF.

4. A clock signal control circuit comprising:

a plurality of amplifier circuit elements each amplifying a clock signal applied thereto; and

a plurality of switching elements each switching passage of the clock signal on and off, wherein

said plurality of amplifier circuit elements are connected in a series fashion through said switching elements that are switched on; and

said switching elements that are switched on are selected, thereby allowing a direction in which said clock signal is traveling through said plurality of amplifier circuit elements to be switched between a forward direction and a backward direction.

5. The clock signal control circuit as defined in claim 4, wherein

said amplifier circuit element comprises an inverter circuit; and

said switching element comprises a MOS semiconductor switch.

6. The clock signal control circuit as defined in claim 4, wherein said switching element comprises N-type channel MOS transfer gate and P-type channel MOS transfer gate, said transfer gates being controlled on and off according to the direction in which the clock signal is traveling.

7. The clock signal control circuit as defined in claim 4, wherein said switching elements are disposed in parallel two lines with said amplifier circuit elements intervening between said two lines, and wherein any of said forward and backward directions is selected by selectively establishing a meander-like path of the series fashion.

8. The clock signal control circuit as defined in claim 4, wherein one of the two directions is established by connecting adjacent two of said amplifier circuit elements via one of said switching elements selected to be ON to form one meander-like path, while the other of the two direction is established by connecting said adjacent two amplifier circuit elements via another one of said switching elements selected to be ON disposed opposing to said one of said switching elements now selected to be OFF.

9. A delay circuit comprising:

(a) a first group of switching elements connected in series between a first input terminal and a first output terminal and including switching elements alternately controlled to be switched on and off by a control signal, or by said control signal and a complementary signal thereof for switching passage of a clock signal on and off;

(b) a second group of switching elements connected in series between a second input terminal and a second output terminal and including switching elements alternately controlled to be switched on and off by the control signal, or by said control signal the complementary signal thereof for switching passage of the clock signal on and off; and

(c) a plurality of amplifier circuit elements connected between the respective junction nodes of the adjacent switching elements of the first group and the respective corresponding junction nodes of the adjacent switching elements of the second group in such a way that one of said plurality amplifier circuit elements is connected forwardly or reversely alternately one to another,

(d) wherein said plurality of amplifier circuit elements are connected in a series fashion through said switching elements that are switched on, and are shared by respective signal paths (i) between said first input terminal and said first output terminal and (ii) between said second input terminal and said second output terminal, and

(e) wherein a direction in which the clock signal is traveling along said respective signal paths may be switched between a first direction from said first input terminal toward said first output terminal and a second direction from said second input terminal toward said second output terminal, by selecting said switching elements that are switched on.

10. A synchronous delay circuit comprising a first delay circuit and a second delay circuit, each delay circuit as defined in claim 9, the first and second delay circuits being control led by the control signal so that the direction in which a clock signal is traveling may be switched between the forward direction and the backward direction,

said synchronous delay circuit including:

an input buffer circuit to which an input clock signal is applied;

a third delay circuit configured for delaying an output of said input buffer circuit;

a frequency divider configured for dividing the output of said input buffer circuit by half,

an output of said frequency divider and its reversed version being fed to said first and second delay circuits as the control signal and the complementary signal thereof, respectively, and an output of said third delay circuit being fed to said respective first input terminals of said first and second delay circuits;

a logical gate circuit to which the output signals of said first and second delay circuits provided through their respective output terminals are applied; and

an output buffer circuit to which an output of said logical gate circuit is applied and which provides an output clock to be fed to appropriate clocking destination.

11. A delay circuit comprising:

(a) a first group of switching elements including a first type of switching elements and a second type of switching elements controlled to be switched on and off by a control signal and a complementary signal thereof, said switching elements of the first type and said switching elements of the second type being connected in series from a first input terminal toward a first output terminal such that each switching element of one type is followed by each switching element of the other type in an alternate manner;

(b) a second group of switching elements including a second type of switching elements and a first type of switching elements controlled to be switched on and off by the control signal and the complementary signal thereof, said switching elements of the second type and said switching elements of the first type being connected in series from a second input terminal located on the side of said first input terminal toward a second output terminal located on the side of said first output terminal such that each switching element of one type is followed by each switching element of the other type in an alternate manner; and

(c) a plurality of amplifier circuit elements connected between each respective junction node of the adjacent switching elements in said first group of switching elements and each respective corresponding junction node of the adjacent switching elements in the second group of switching elements, each alternate one of said plurality of amplifier circuit elements having its input terminal and its output terminal connected (i) between said each respective junction node of the adjacent switching elements in said first group of switching element and said each respective junction node of the adjacent switching elements in said second group of switching elements and (ii) between said each respective junction node of the adjacent switching elements in said second group of switching elements and said each respective junction node of the adjacent switching elements in said first group of switching elements, respectively.

12. The delay circuit as defined in claim 11, wherein

(i) when said control signal is active, it causes the switching elements of the first type to be switched on, allowing the clock signal applied to said first input terminal to travel from said first input terminal toward said first output terminal through said switching elements of the first type that are switched on and said amplifier circuit elements, and

(ii) when the complementary signal of said control signal is active, it causes the switching elements of the second type to be switched on, allowing the clock signal applied to said second input terminal to travel from said second input terminal toward said second output terminal through said switching elements of the second type that are switched on and said amplifier circuit elements.

13. The delay circuit as defined in claim 11, wherein

(d) said first group of switching elements are connected in series between said first input terminal and said first output terminal through a first-stage switching element of the first type, followed by a second-stage switching element of the second type, followed further in an alternate fashion, and finally followed by a final-stage switching element of the first type;

and

(e) said second group of switching elements are connected in series between said second input terminal and said second output terminal through a first-stage switching element of the second type, followed by a second-stage switching element of the first type, followed further in an alternate fashion, and finally followed by a final-stage switching element of the second type, (f) wherein

(i) when said control signal is active, it causes the switching element of the first type in the first and second group of switching elements to be switched on, allowing the clock signal applied to said first input terminal to travel through said switching elements of the first type thus switched on and through said amplifier circuit elements and then appear on said first output terminal, and

(ii) when the complementary signal of said control signal is active, it causes the switching elements of the second type in the first and second group of switching elements to be switched on, allowing the clock signal to travel through said switching elements of the second type and through said amplifier circuit elements and appear on said second output terminal.

14. A synchronous delay circuit comprising:

a first delay circuit and a second delay circuit, each delay circuit as defined in claim 11, the first and second delay circuits being controlled by the control signal so that the direction in which a clock signal is traveling may be switched between the forward direction and the backward direction,

said synchronous delay circuit including;

an input buffer circuit to which an input clock signal is applied;

a third delay circuit configured for delaying an output of said input buffer circuit;

a frequency divider configured for dividing the output of said input buffer circuit by half,

an output of said frequency divider and its reversed version being fed to said first and second delay circuits as the control signal and the complementary signal thereof, respectively, and an output of said third delay circuit being fed to said respective first input terminals of said first and second delay circuits;

a logical gate circuit to which the output signals of said first and second delay circuits provided through their respective output terminals are applied; and

an output buffer circuit to which an output of said logical gate circuit is applied and which provides an output clock to be fed to appropriate clocking destination.

15. A delay circuit comprising:

(a) a first group of switching elements including a first type of switching elements and a second type of switching elements controlled to be switched on and off by a control signal when it is active, each alternate one of said switching elements of the first type and said switching elements of the second type being connected in series between a first input terminal and a first output terminal along this direction;

(b) a second group of switching elements including a second type of switching elements and a first type of switching elements controlled to be switched on and off, respectively, by the control signal when it is inactive, each alternate one of said switching elements of the second type and said switching elements of the first type being connected in series between a second input terminal located on the side of said first output terminal and a second output terminal located on the side of said first input terminal along this direction; and

(c) a plurality of amplifier circuit elements connected between each respective junction node of the adjacent switching elements in said first group of switching elements and each respective corresponding junction node of the adjacent switching elements in the second group of switching elements, each alternate one of said plurality of amplifier circuit elements having its input terminal and its output terminal connected in an alternate fashion, (i) between said each respective junction node of the adjacent switching elements in said first group of switching element and said each respective junction node of the adjacent switching elements in said second group of switching elements and (ii) between said each respective junction node of the adjacent switching elements in said second group of switching elements and said each respective junction node of the adjacent switching elements in said first group of switching elements, respectively.

16. A synchronous delay circuit comprising:

a first delay circuit and a second delay circuit, each delay circuit as defined in claim 15, the first and second delay circuits being controlled by the control signal so that the direction in which a clock signal is traveling may be switched between the forward direction and the backward direction,

said synchronous delay circuit including;

an input buffer circuit to which an input clock signal is applied

a third delay circuit configured for delaying an output of said input buffer circuit;

a frequency divider configured for dividing the output of said input buffer circuit by half,

an output of said frequency divider and its reversed version being fed to said first and second delay circuits as the control signal and the complementary signal thereof, respectively, and an output of said third delay circuit being fed to said respective first input terminals of said first and second delay circuits;

a logical gate circuit to which the output signals of said first and second delay circuits provided through their respective output terminals are applied; and

an output buffer circuit to which an output of said logical gate circuit is applied and which provides an output clock to be fed to appropriate clocking destination.

17. A delay circuit comprising:

(a) a first group of switching elements including P-type channel MOS transistors and N-type channel MOS transistors connected in series between a first input terminal and a first output terminal in such a way that each alternate one of the transistors of one type is followed by each alternate one of the transistors of the other type, and controlled so that the transistors of the one type may be turned off when the transistors of the other type are turned on, in accordance with a predetermined value of a control signal;

(b) a second group of switching elements including P-type channel MOS transistors and N-type channel MOS transistors connected in series between a second input terminal located on the side of said first output terminal and a second output terminal located on the side of said first input terminal in such a way that each alternate one of the transistors of one type is followed by each alternate one of the transistors of the other type, and control led so that the transistors of the one type may be turned off when the transistors of the other type are turned on, in accordance with a predetermined value of a complementary signal of said control signal that is reversed by an inverter; and

(c) a plurality of inverter circuits connected between each respective junction node of the adjacent transistors in said first group of switching elements and each respective corresponding junction node of the adjacent transistors in the second group of switching elements, each alternate one of said plurality of inverter circuits having its input terminal and its output terminal connected, in an alternate fashion, (i) between said each respective junction node of the adjacent transistors in said first group of switching element and said each respective junction node of the adjacent transistors in said second group of switching elements and (ii) between said each respective junction node of the adjacent transistors in said second group of switching elements and said each respective junction node of the adjacent transistors in said first group of switching elements, respectively.

18. The delay circuit as defined in claim 17, wherein those transistors connected in series along a forward signal traveling path from said first input terminal toward said first output terminal, and those transistors connected in series along a backward signal traveling path from said second input terminal toward said second output terminal have different current driving capabilities.

19. A synchronous delay circuit comprising:

a first delay circuit and a second delay circuit, each delay circuit as defined in claim 17, the first and second delay circuits being control led by the control signal so that the direction in which a clock signal is traveling may be switched over between the forward direction and the backward direction,

said synchronous delay circuit including;

an input buffer circuit to which an input clock signal is applied;

a third delay circuit configured for delaying an output of said input buffer circuit;

a frequency divider configured for dividing the output of said input buffer circuit by half,

an output of said frequency divider and its inversed version being fed to said first and second delay circuits as the control signal and the complementary signal thereof, respectively, and an output of said third delay circuit being fed to said respective first input terminals of said first and second delay circuits;

a logical gate circuit to which the output signals of said first and second delay circuits provided through their respective output terminals are applied; and

an output buffer circuit to which an output of said logical gate circuit is applied and which provides an output clock to be fed to appropriate clocking destination.