Circuit and method for controlling an output of a ring oscillator

• US 6,275,117 B1
• Filed: 12/18/1998
• Issued: 08/14/2001
• Est. Priority Date: 12/18/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Abugharbieh, Khaldoon, Min, Sung-Ki
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/216,460
• Time in Patent Office: 970 Days
• Field of Search: 327/276, 327/158, 327/281, 331/57, 331/34, 323/313
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A circuit and method configured to generate a variable impedance. The circuit may comprise a voltage controlled resistor configured to generate the variable impedance in response to (i) a first transistor configured to receive a first control signal and (ii) a bias transistor configured to receive a bias signal. In one example, the variable impedance may be generated in further response to a clamp transistor.

Claims

1. A circuit configured to generate a output signal having a frequency comprising:

a voltage controlled resistor configured to generate a variable impedance in response to (i) a first transistor configured to receive a control signal and (ii) a bias transistor configured to receive a bias signal, wherein said bias signal causes said bias transistor to remain in a linear region and said bias transistor is weak compared to said first transistor and is configured to improve said variable impedance when said first transistor is saturated.

2. The circuit according to claim 1, wherein said variable impedance is generated in further response to a clamp transistor.

3. The circuit according to claim 1, further comprising:

a ring oscillator configured to generate said output signal in further response to (i) a plurality of said voltage controlled resistors and (ii) an input signal.

4. The circuit according to claim 3, wherein said frequency of said output signal is proportional to a ratio of said plurality of voltage controlled resistors.

5. The circuit according to claim 3, further comprising:

a pump-up circuit and a pump-down circuit configured to generate said input signal.

6. The circuit according to claim 2, wherein said output signal has a controlled swing in response to said clamp transistor.

13. The circuit according to claim 2, wherein said bias transistor is further configured to improve said variable impedance when said clamp transistor is cut-off.

14. The circuit according to claim 2, wherein said bias transistor is further configured to provide a low impedance configured to provide proper oscillation of said output signal when said clamp transistor is cut-off.

18. The circuit according to claim 1, wherein said bias transistor is between 1% to 30% as strong as said first transistor.

7. A method configured to generate a variable impedance output signal comprising the steps of:

(a) controlling a first device;

(b) controlling a bias device, wherein said bias device is weaker than said first device; and

(c) generating said variable impedance output signal in response to (i) a control signal and (ii) a bias signal, wherein step (c) comprises causing step (a) to remain in a linear region and step (b) to improve said variable impedance output signal when said first device is saturated.

8. The method according to claim 7, further comprising the step of:

generating said output signal in further response to (i) a plurality of said variable impedances and (ii) an input signal.

9. The method according to claim 8, wherein said variable impedance output signal has a controlled swing in response to a clamping device.

10. The method according to claim 9, further comprising the step of:

converting said output signal to a clock signal having a frequency.

11. The method according to claim 10, wherein a frequency of said clock signal is proportional to a ratio of said plurality of impedances.

15. The method according to claim 7, wherein step (c) further comprises improving said variable impedance when a clamp device is cut-off.

16. The method according to claim 7, wherein step (c) further comprises providing a low impedance to provide proper oscillation of said variable impedance output signal when a clamp device is cut-off.

12. A circuit configured to generate a variable impedance output signal comprising:

a voltage controlled resistor configured to generate said variable impedance output signal in response to (i) a first transistor configured to receive a control signal, (ii) a bias transistor configured to receive a bias signal, wherein said bias transistor is weaker than said first transistor and (iii) a clamp transistor, wherein said bias signal causes said bias transistor to remain in a linear region and said bias transistor is configured to improve said variable impedance output signal when said first transistor is saturated and said clamp transistor is cut-off.

17. The circuit according to claim 12, wherein said bias transistor is further configured to provide a low impedance configured to provide proper oscillation of said variable impedance output signal when said clamp transistor is cut-off.

19. A circuit configured to generate an output signal having a frequency comprising:

a voltage controlled resistor configured to generate a variable impedance in response to (i) a first transistor configured to receive a control signal and (ii) a bias transistor configured to receive a bias signal, wherein said bias signal causes said bias transistor to remain in a linear region and said bias transistor is between 1% to 30% as strong as said first transistor and is configured to improve said variable impedance when said first transistor is saturated.

20. An apparatus configured to generate an output signal having a frequency comprising:

means for generating a control signal;

means for generating a bias signal, wherein said bias signal generating means is weaker than said control signal generating means; and

means for generating a variable impedance in response to (i) said control signal and (ii) said bias signal, wherein (i) said bias signal causes said control signal generating means to remain in a linear region and (ii) said bias signal generating means is weaker than said control signal generating means and is configured to improve said variable impedance when said control signal generating means is saturated.