Semiconductor piezoresistor

• US 6,275,137 B1
• Filed: 02/08/2000
• Issued: 08/14/2001
• Est. Priority Date: 02/08/2000
• Status: Expired due to Term

• Current Assignee: Pall Corporation (Danaher Corporation)
• Original Assignee: Boston MicroSystems, Inc. (Danaher Corporation)
• Inventors: Moustakas, Theodore D., Tuller, Harry L., Doppalapudi, Dharanipal, Mlcak, Richard
• Primary Examiner(s): Easthom, Karl D.
• Application Number:
  US09/500,408
• Time in Patent Office: 553 Days
• Field of Search: 338/2, 338/5, 338/47, 338/101, 257/417, 296/101, 296/20, 296/21
• US Class Current: 338/2
• CPC Class Codes: G01L 1/2293 of the semi-conductor type semi-conductor devices controllable by variations of applied mechanical force H01L29/84
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: Y10T 29/49099 Coating resistive material on a base
• CPC Class Codes: Y10T 29/49101 Applying terminal

Abstract

A piezoresistor having a base substrate with a quantum well structure formed on the base substrate. The quantum well structure includes at least one quantum well layer bounded by barrier layers. The barrier layers are formed from a material having a larger bandgap than the at least one quantum well layer.

Claims

1. A piezoresistor comprising:

a base substrate; and

a quantum well structure formed on the base substrate, the quantum well structure comprising at least one quantum well layer bounded by barrier layers, the barrier layers being formed from a material having a larger bandgap than the at least one quantum well layer, the at least one quantum well layer having a thickness of 30 Å

or less.

2. The piezoresistor of claim 1 in which each quantum well layer is 5 Å

to 30 Å

thick.

3. The piezoresistor of claim 1 in which the barrier layers in the quantum well structure are more than 5 Å

thick.

4. The piezoresistor of claim 1 in which the barrier layers are 5 Å

to 50 Å

thick.

5. The piezoresistor of claim 1 in which at least a portion of the base substrate is formed of a single crystal material.

6. The piezoresistor of claim 1 in which the quantum well structure has 5 to 10 quantum well layers.

7. The piezoresistor of claim 1 in which selected layers in the quantum well structure are doped.

8. The piezoresistor of claim 1 in which the layers of the quantum well structure are formed by epitaxial growth.

9. The piezoresistor of claim 1 in which the base substrate is a single crystal.

10. The piezoresistor of claim 1 in which the base substrate is a mechanical element of a sensor.

11. The piezoresistor of claim 10 in which the mechanical element is micromachined.

12. The piezoresistor of claim 1 in which the base substrate is a thin film.

13. The piezoresistor of claim 1 in which the at least one quantum well layer is formed from a material selected from the group consisting of group IV, group III-V and group II-VI semiconductor materials.

14. The piezoresistor of claim 1 in which the barrier layers are formed from an insulating material.

15. The piezoresistor of claim 1 in which the barrier layers are formed from a material selected from the group consisting of group IV, group III-V and group II-VI materials.

16. A piezoresistor comprising:

a single crystal base substrate; and

a quantum well structure formed on the base substrate, the quantum well structure having alternating semiconductor barrier and quantum well layers, the barrier layers being formed from a material having a larger bandgap than the quantum well layers, the quantum well layers having a thickness of 30 Å

or less.

17. A piezoresistor comprising:

a base substrate, at least a portion of the base substrate being formed of a single crystal material; and

a quantum well structure formed on the single crystal portion of the base substrate, the quantum well Structure having alternating semiconductor barrier and quantum well layers, the barrier layers being formed from a material having a larger bandgap than the quantum well layers, the quantum well layers having a thickness of 30 Å

or less.

18. A method of forming a piezoresistor comprising the steps of:

providing a base substrate; and

depositing at least one quantum well layer bounded by barrier layers on the base substrate to form a quantum well structure, the barrier layers being formed from a material having a larger bandgap than the at least one quantum well layer, the at least one quantum well layer having a thickness of 30 Å

or less.

19. The method of claim 18 further comprising the step of forming each quantum well layer to a thickness of 5 Å

to 30 Å

.

20. The method of claim 18 further comprising the step of depositing barrier layers that are more than 5 Å

thick.

21. The method of claim 19 further comprising the step of depositing barrier layers that are 5 Å

to 50 Å

thick.

22. The method of claim 18 further comprising the step of forming at least a portion of the base substrate from a single crystal material.

23. The method of claim 18 further comprising the step of depositing 5 to 10 quantum well layers in the quantum well structure.

24. The method of claim 18 in which the step of depositing the barrier and quantum well layers further comprises epitaxially growing the layers.

25. The method of claim 18 further comprising the step of doping selected layers in the quantum well structure.

26. The method of claim 18 further comprising the step of forming the base substrate from a single crystal.

27. The method of claim 18 further comprising the step of forming the base substrate from a mechanical element of a sensor.

28. The method of claim 27 further comprising the step of micromachining the mechanical element.

29. The method of claim 18 further comprising the step of forming the base substrate into a film.

30. A method of forming a piezoresistor comprising the steps of:

providing a single crystal base substrate; and

depositing alternating semiconductor barrier and quantum well layers on the base substrate to form a quantum well structure, the barrier layers being formed from a material having a larger bandgap than the quantum well layers, the quantum well layers having a thickness of 30 Å

or less.