Multi-state memory

• US 6,275,419 B1
• Filed: 10/13/2000
• Issued: 08/14/2001
• Est. Priority Date: 01/14/1992
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/688,068
• Time in Patent Office: 305 Days
• Field of Search: 365/185.01, 365/185.26, 365/185.28, 365/185.29, 365/185.18
• US Class Current: 365/185.29
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-stage compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1. A method of operating a memory which comprises a plurality of word lines, and a plurality of EEPROM memory cells, each cell uniquely associated with one word line and one bit line, each memory cell having a floating gate electrode, a steering electrode, and an erase electrode, said method comprising the steps of:

selecting one or more of said memory cells along a row;

controlling the magnitude of a steering voltage applied to said steering electrodes of said selected one or more memory cells, on a cell by cell basis;

establishing erase potentials on said selected one or more memory cells, thereby removing charge from said floating gates of said selected one or more memory cells,

wherein the magnitude of electron removal from each floating gate is established on a cell by cell basis by the magnitude of the steering potential applied to its associated steering electrode.

2. A method as in claim 1 which further comprises the steps of iteratively:

pulsing said erase potentials;

determining which cells have been adequately erased; and

again pulsing said erase potentials for those cells which have not been adequately erased and terminating application of said erase potentials on cells which have been adequately erased.

3. A method as in claim 1 wherein said erasure serves to write data to said selected memory cells.

4. A method as in claim 3 wherein said data is represented by less or equal charge on said floating gates than the amount of charge on said floating gates prior to said erasure.

5. A method as in claim 4 wherein said data comprises multi-state data.

6. A method as in claim 4 wherein establishing said amount of charge on said floating gates prior to said erasure is accomplished by hot electron programming from a source region of said memory cell to said floating gate of said memory cell.

7. A method as in claim 1 which further comprises the steps of:

dividing said word line of memory cells into a plurality of subsets of memory cells;

simultaneously erasing each of said subsets of memory cells; and

terminating the erasure of each of said subsets of memory cells on a cell by cell basis when all memory cells in a given subset have been adequately erased, regardless of whether erasure of others of said subsets of memory cells has been completed.

8. A method as in claim 2 wherein said erase serves to write data to said selected memory cells.