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Four transistor SRAM cell with improved read access

  • US 6,275,433 B1
  • Filed: 08/30/2000
  • Issued: 08/14/2001
  • Est. Priority Date: 08/30/2000
  • Status: Expired due to Fees
First Claim
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1. A memory cell, comprising:

  • first and second output nodes;

    a first transistor coupled between a first power supply node and the first output node;

    a first load coupled between the first output node and a second power supply node;

    a second load coupled between the first power supply node and the second output node; and

    a second transistor coupled between the second output node and the second power supply node, a gate terminal of the first transistor being coupled to the second output node, and a gate terminal of the second transistor being coupled to the first output node.

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