Four transistor SRAM cell with improved read access

• US 6,275,433 B1
• Filed: 08/30/2000
• Issued: 08/14/2001
• Est. Priority Date: 08/30/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/651,632
• Time in Patent Office: 349 Days
• Field of Search: 365/205, 365/203, 365/207, 365/208, 365/230.06, 365/233
• US Class Current: 365/205
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A memory cell comprises first and second output nodes, a first transistor coupled between a first power supply node and the first output node, a first load coupled between the first output node and a second power supply node, a second load coupled between the first power supply node and the second output node, and a second transistor coupled between the second output node and the second power supply node. A gate terminal of the first transistor is coupled to the second output node, and a gate terminal of the second transistor is coupled to the first output node.

Claims

1. A memory cell, comprising:

first and second output nodes;

a first transistor coupled between a first power supply node and the first output node;

a first load coupled between the first output node and a second power supply node;

a second load coupled between the first power supply node and the second output node; and

a second transistor coupled between the second output node and the second power supply node,

a gate terminal of the first transistor being coupled to the second output node, and a gate terminal of the second transistor being coupled to the first output node.

2. The memory cell of claim 1, wherein the first and second loads comprise first and second resistors.

3. The memory cell of claim 2, wherein the first and second resistors comprise first and second resistors each having a value between approximately 100k ohms and approximately 200k ohms.

4. The memory cell of claim 1, further comprising:

a first access transistor coupled between the first output node and a first bit line; and

a second access transistor coupled between the second output node and a second bit line,

the first and second access transistors each comprising a gate terminal coupled to an access signal line, the first and second access transistors adapted to couple the first and second output nodes to the first and second bit lines, respectively, in response to an access signal on the access signal line.

5. The memory cell of claim 4, wherein the first and second loads comprise first and second resistors.

6. The memory cell of claim 5, wherein the first and second resistors comprise first and second resistors each having a value between approximately 100k ohms and approximately 200 k ohms.

7. The memory cell of claim 1, wherein the first transistor comprises a p-channel transistor and the second transistor comprises an n-channel transistor.

8. The memory cell of claim 7, wherein the first and second loads comprise first and second resistors.

9. The memory cell of claim 8, wherein the first and second resistors comprise first and second resistors each having a value between approximately 100 k ohms and approximately 200 k ohms.

10. The memory cell of claim 7, wherein the first power supply node comprises a positive power supply node and the second power supply node comprises a power supply electrical ground node.

11. The memory cell of claim 1, wherein the first power supply node comprises a positive power supply node and the second power supply node comprises a power supply electrical ground node.

12. The memory cell of claim 11, wherein the first and second loads comprise first and second resistors.

13. The memory cell of claim 12, wherein the first and second resistors comprise first and second resistors each having a value between approximately 100 k ohms and approximately 200 k ohms.

14. A sense amplifier, comprising:

first and second output nodes;

a first transistor coupled between a first power supply node and the first output node;

a second transistor coupled between the first output node and a second power supply node, the second transistor having a gate terminal coupled to a first bit line;

a third transistor coupled between the first power supply node and the second output node;

a fourth transistor coupled between the first power supply node and the second output node, the fourth transistor having a gate terminal coupled to a clock signal line; and

a fifth transistor coupled between the second output node and the second power supply node, the fifth transistor having a gate terminal coupled to a second bit line,

the sense amplifier adapted to provide first and second output signals at the first and second output nodes, respectively, in response to signals on the first and second bit lines and a clock signal on the clock signal line.

15. The sense amplifier of claim 14, further comprising a sixth transistor coupled between the second transistor and the second power supply node, the sixth transistor also being coupled between the first transistor and the second power supply node, the sixth transistor having a gate terminal coupled to the clock signal line.

16. The sense amplifier of claim 15, wherein the first, third and fourth transistors each comprise a p-channel transistor, and wherein the first and third transistors each have a gate terminal coupled to the second power supply node.

17. The sense amplifier of claim 16, wherein the first power supply node comprises a positive power supply node and the second power supply node comprises a power supply electrical ground node.

18. The sense amplifier of claim 14, wherein the first, third and fourth transistors each comprise a p-channel transistor, and wherein the first and third transistors each have a gate terminal coupled to the second power supply node.

19. The sense amplifier of claim 18, wherein the first power supply node comprises a positive power supply node and the second power supply node comprises a power supply electrical ground node.

20. A sense amplifier, comprising:

first and second output nodes;

a first load coupled between a first power supply node and the first output node;

a second load coupled between the first power supply node and the second output node;

a first input transistor coupled between the first output node and a second power supply node, the first in put transistor having a gate terminal coupled to a first bit line;

a second input transistor coupled between the second output node and the second power supply node, the second input transistor having a gate terminal coupled to a second bit line; and

a pre-charge transistor coupled between the first power supply node and the second output node, the pre-charge transistor having a gate terminal coupled to a clock signal line, the pre-charge transistor adapted to couple the second output node to the first power supply node during a first phase of a clock signal on the clock signal line.

21. The sense amplifier of claim 20, further comprising:

an activating transistor coupled between the first input transistor and the second power supply node and coupled between the second input transistor and the second power supply node, the activating transistor having a gate terminal coupled to the clock signal line,

the activating transistor adapted to couple the first and second input transistors to the second power supply node during a second phase of the clock signal on the clock signal line.

22. The sense amplifier of claim 21, wherein the first and second loads comprise first and second p-channel transistors, each of the first and second p-channel transistors having a gate terminal coupled to the second power supply node.

23. The sense amplifier of claim 22, wherein the first power supply node is a positive power supply node and the second power supply node comprises a power supply electrical ground node.

24. The sense amplifier of claim 20, wherein the first and second loads comprise first and second p-channel transistors, each of the first and second p-channel transistors having a gate terminal coupled to the second power supply node.

25. The sense amplifier of claim 23, wherein the first power supply node comprises a positive power supply node and the second power supply node comprises a power supply electrical ground node.

26. The sense amplifier of claim 20, wherein the first power supply node comprises a positive power supply node and the second power supply node comprises a power supply electrical ground node.

27. A memory cell sense circuit, comprising:

a sense amplifier, having;

first and second sense amplifier output nodes;

a sense amplifier pre-charge transistor coupled between a first power supply node and the second sense amplifier output node, the pre-charge transistor having a gate terminal coupled to a clock signal line, the pre-charge transistor adapted to couple the second sense amplifier output node to the first power supply node during a first phase of a first clock signal on the clock signal line;

a first input transistor coupled between the first sense amplifier output node and a sense amplifier activating node, the first input transistor having a gate terminal coupled to a first bit line;

a second input transistor coupled between the second sense amplifier output node and the sense amplifier activating node, the second input transistor having a gate terminal coupled to a second bit line; and

a sense amplifier activating transistor coupled between the second amplifier activating node and a second power supply node, the sense amplifier activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors to the second power supply node during a second phase of the first clock signal on the clock signal line;

a first driver circuit, having;

a first driver output node;

a first driver pre-charge transistor coupled between the first power supply node and the first driver output node, the first driver pre-charge transistor having a gate terminal coupled to the clock signal line and adapted to couple the first driver output node to the first power supply node during a first phase of a second clock signal on the clock signal line;

a first input transistor coupled between the first power supply node and a first driver activating node, the first input transistor of the first driver having a gate terminal coupled to the first sense amplifier output node;

a second input transistor coupled between the first driver output node and the first driver activating node, the second input transistor of the first driver having a gate terminal coupled to the second sense amplifier output node; and

a first driver activating transistor coupled between the first driver activating node and the second power supply node, the first driver activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors of the first driver to the second power supply node during a second phase of the second clock signal in the clock signal line;

a second driver circuit, having,

a second driver output node;

a second driver pre-charge transistor coupled between the first power supply node and the second driver output node, the second driver pre-charge transistor having a gate terminal coupled to the clock signal line and adapted to couple the second driver output node to the first power supply node during a first phase of the second clock signal on the clock signal line;

a first input transistor coupled between the first power supply node and a second driver activating node, the first input transistor of the second driver having a gate terminal coupled to the second sense amplifier output node;

a second input transistor coupled between the second driver output node and the second driver activating node, the second input transistor of the second driver having a gate terminal coupled to the first sense amplifier output node; and

a second driver activating transistor coupled between the second driver activating node and the second power supply node, the second driver activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors of the second driver to the second power supply node during a second phase of the second clock signal on the clock signal line; and

a driver output circuit, having;

a driver circuit output node;

a driver circuit pre-charge transistor coupled between the first power supply node and the driver circuit output node, the driver circuit pre-charge transistor having a gate terminal coupled to the clock signal line and adapted to couple the driver circuit output node to the first power supply node during a first phase of a third clock signal on the clock signal line;

a first input transistor coupled between the first power supply node and a driver circuit activating node, the first input transistor of the driver circuit having a gate terminal coupled to the second driver output node;

a second input transistor coupled between the driver circuit output node and the driver circuit activating node, the second input transistor of the driver circuit having a gate terminal coupled to the first driver output node; and

a driver circuit activating transistor coupled between the driver circuit activating node and the second power supply node, the driver circuit activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors of the driver circuit to the second power supply node during a second phase of the third clock signal on the clock signal line.

28. A memory cell sense circuit, comprising:

a sense amplifier coupled to first and second bit lines and having first and second sense amplifier output nodes;

a first driver circuit coupled to the first and second sense amplifier output nodes and having a first driver output node;

a second driver circuit coupled to the first and second sense amplifier output nodes and having a second driver output node; and

an output driver circuit coupled to the first and second driver output nodes and having an output driver output node,

the sense amplifier having a pre-charge transistor coupled to the second sense amplifier output node and adapted to pre-charge the second sense amplifier output node to approximately a first power supply potential, and

each of the first driver circuit, the second driver circuit and the output driver circuit having a pre-charge transistor coupled to its respective output node and adapted to pre-charge its respective output node to approximately the first power supply potential.