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Memory access controller

  • US 6,275,877 B1
  • Filed: 10/27/1998
  • Issued: 08/14/2001
  • Est. Priority Date: 10/27/1998
  • Status: Expired due to Term
First Claim
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1. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

  • a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing a buffer descriptor for each required access transaction for each channel, said descriptor containing a starting address indicator in system memory for the transaction a length indicator for data involved in the access transaction, and a wrap bit;

    a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels, said component performing access for a channel based on successive buffer descriptors until access is performed for a descriptor for which a wrap bit is present, the component returning to an initial buffer descriptor for the channel after an access for the wrap-bit-containing descriptor; and

    a channel arbiter which selects the channel for which said component provides access control at a given time.

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