Memory access controller

• US 6,275,877 B1
• Filed: 10/27/1998
• Issued: 08/14/2001
• Est. Priority Date: 10/27/1998
• Status: Expired due to Term

• Current Assignee: Digi International Inc.
• Original Assignee: Digi International Inc.
• Inventors: Duda, James
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/179,946
• Time in Patent Office: 1,022 Days
• Field of Search: 710/23, 710/72, 710/33, 709/229, 709/230
• US Class Current: 710/23
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A direct memory access controller is provided which utilizes a single dedicated controller to control all or substantially all memory accesses in a computer system, both memory-to-memory accesses within the system and transfers between system memory and various system peripherals. At least portions of the controller are time shared by various channels, each channel performing data transfers in a selected direction between a system memory component and a second component which may be a peripheral, another memory component or the like. An arbiter is provided as part of the controller for determining the channel using shared resources at any given time. Where one of the peripherals is a variable length packetized data source, multiple subchannels may be provided for transfers of data for such source into system memory, each such subehannel being for transfers to buffers of different size. Efficient memory utilization is achieved by determining the size of an incoming variable length packet and having the transfer performed through the channel servicing the smallest available buffer in which incoming variable length packetized data will fit.

Claims

1. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing a buffer descriptor for each required access transaction for each channel, said descriptor containing a starting address indicator in system memory for the transaction a length indicator for data involved in the access transaction, and a wrap bit;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels, said component performing access for a channel based on successive buffer descriptors until access is performed for a descriptor for which a wrap bit is present, the component returning to an initial buffer descriptor for the channel after an access for the wrap-bit-containing descriptor; and

a channel arbiter which selects the channel for which said component provides access control at a given time.

2. An access controller as claimed in claim 1 wherein each buffer descriptor includes at least one bit indicating that the buffer descriptor is the last descriptor of a selected group of descriptions.

3. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing a buffer descriptor for each required access transaction for each channel, said descriptor containing a starting address indicator in system memory for the transaction, a length indicator for data involved in the access transaction and a full bit (F-bit) which is set when the corresponding buffer is full;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels, the component not attempting to perform a read access to a buffer for which the F-bit is not set or a write access to a buffer for which the F-bit is set; and

a channel arbiter which selects the channel for which said component provides access control at a given time.

4. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing a buffer descriptor for each required access transaction for each channel, said descriptor containing a starting address indicator in system memory for the transaction, a length indicator for data involved in the access transaction and an interrupt (I-bit);

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;

a CPU which issues access instructions to the access controller, the controller issuing an interrupt to the CPU after completion of an access transaction for which the corresponding descriptor has the I-bit present; and

a channel arbiter which selects the channel for which said component provides access control at a given time.

5. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing selected information on each required access transaction for each channel and configuration registers for each channel,

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels; and

a channel arbiter which selects the channel for which said component provides access control at a given time.

6. An access controller as claimed in claim 5 wherein one of said configuration registers for each channel identifies the start address for the buffer descriptors for the corresponding channel.

7. An access controller as claimed in claim 5 wherein one of said configuration registers for each channel is a control register having fields which control various functions.

8. An access controller as claimed in claim 7 wherein said control register contains a priority field, the priority indicated by said priority field being a factor in channel selection by said channel arbiter.

9. An access controller as claimed in claim 7 wherein said control register contains a field indicating a mode of memory access to be performed by the channel.

10. An access controller as claimed in claim 7 wherein said control register contains a field indicating a quantity of data to be transferred for the channel during each memory access.

11. An access controller as claimed in claim 7 wherein said control register contains a field indicating an offset address for an active channel buffer descriptor from a buffer descriptor start address for the channel.

12. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels; and

a channel arbiter which selects the channel for which said component provides access control at a given time; and

wherein at least one of said channels is for transferring data in at least one direction between a memory and a peripheral through a serial port, and including a serial module through which the data to be transferred passes, said module performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/peripheral receiving an output from the module.

13. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels; and

a channel arbiter which selects the channel for which said component provides access control at a given time; and

wherein at least one of said channels is for transferring data in at least one direction between a memory and a peripheral through a parallel port, and including a parallel module through which the data to be transferred passes, said module performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/peripheral receiving an output from the module.

14. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;

a channel arbiter which selects the channel for which said component provides access control at a given time; and

wherein at least one of said channels is for transferring packetized data in at least one direction between a memory and a packetized data source through a packetized data port, and including a packetized data module through which the data to be transferred passes, said module performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/packetized data source receiving an output from the module.

15. An access controller as claimed in claim 14 wherein data packets from said packetized data source may be of variable length, wherein a said channel for transferring data packets from the packetized data source to memory is divided into N channels, N being an integer greater than one, each of said N channels being for memory buffers of different size, the one of said N channels used for transfer of a received data packet being the channel having the smallest available buffer in which the received data packet will fit.

16. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels; and

a channel arbiter which selects the channel for which said component provides access control at a given time; and

wherein each channel is for memory accesses in one direction between a memory and a second element, wherein said component includes a first component which controls addressing and data transfer for memory accesses through said channels, and at least one second component through which data passes for at least one channel during a memory access for such channel, the second component performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/second element receiving an output from the second component.

17. An access controller as claimed in claim 16 wherein said second element is a peripheral.

18. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels; and

a channel arbiter which selects the channel for which said component provides access control at a given time; and

wherein at least one of said channels if for transfer of data between a first memory and a second memory of said computer system memory, wherein said context memory includes an indication of a start address in one of said memory from which data to be transferred is read out, an indication of a start address in the other of said memory at which the data is to be written and an indication of the quantity of data to be transferred, wherein said component includes at least one first component for controlling the addressing of said memories and at least one second component for controlling data transfers for said memories, and including a holding register for storing the data to be transferred between a read access to said one memory and a write access to said other memory.

19. An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

a context memory storing information relating to the current state of each channel;

a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;

a channel arbiter which selects the channel for which said component provides access control at a given time; and

a bus through which transfers for said system memory pass, said component controlling at least selected data transfers through said bus; and

wherein at least selected memory components of said system memory are connected to transfer data with at least one other system component without passing through said bus, said component providing controls for each such transfer.

20. An access controller as claimed in claim 19 including a main CPU which accesses said system memory through said bus and a second CPU which shares at least a portion of said system memory with said main CPU, said component controlling accesses to said at least a portion of systems memory by said second CPU.

21. An access controller as claimed in claim 19 wherein transfers of data are performed through said bus between an external device and system memory, wherein said component includes a controller which normally interfaces with said context memory to control memory accesses and a module through which accesses are performed, and wherein said module includes elements for passing data between said external device and system memory under control of the external device without substantial involvement of said controller.

22. An access controller for controlling the transfer of variable length packetized data (VLPD) from a VLPD source to a system memory including:

N channels through which said transfer of VLPD may be effected, where N is an integer greater than one, each of said channels controlling transfers to buffers of different size in said system memory, an indicator as to the availability of a buffer for each channel to receive date, a mechanism receiving an indication of the size of a VLPD to be transferred, and a mechanism utilizing said availability indicator and size indication to determine the channel for the smallest available buffer in which the VLPD to be transferred will fit, said controller utilizing the determined channel to store the VLPD in said smallest available buffer.

23. A method for controlling the transfer of variable length packetized data (VLPD) from a VLPD source to a system memory including:

providing N channels though which said transfer of VLPD may be effected, where N is an integer greater than one, each of said channels controlling transfers to buffers of different size in said system memory;

indicating the availability of a buffer for each channel to receive data;

receiving an indication of the size of each VLPD to be transferred;

utilizing said availability indicator and size indication to determine the channel for the smallest available buffer in which the VLPD to be transferred will fit; and

utilizing the determined channel to store the VLPD in said smallest available buffer.