Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture

• US 6,275,894 B1
• Filed: 09/23/1998
• Issued: 08/14/2001
• Est. Priority Date: 09/23/1998
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kuo, Tiao-Hua, Kasa, Yasushi, Leong, Nancy, Chen, Johnny, Van Buskirk, Michael
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Peugh, Brian R.
• Application Number:
  US09/159,489
• Time in Patent Office: 1,056 Days
• Field of Search: 711/5, 711/103, 711/129, 711/1, 711/102, 365/193, 365/185.11, 365/185.13, 365/230.03
• US Class Current: 711/103
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

Claims

1. The bank selector circuit for a non-volatile memory device with a flexible bank partition architecture, comprising:

(a) a memory boundary option designating a memory partition boundary selected from a plurality of predetermined memory partition boundaries, the memory boundary option capable of generating a partition boundary indicator signal based upon the selected memory partition boundary, the memory boundary option comprising a partition indicator circuit capable of designating the selected memory partition boundary that separates the memory into the upper memory bank and the lower memory bank, wherein the partition indicator circuit further comprises;

(i) an upper bank conductive line comprising first and second upper bank conductive line segments separated by an upper bank conductive line gap identifying the selected memory partition boundary, the first upper bank conductive line segment having a first end capable of receiving a DC common voltage, and the second upper bank conductive line segment having a second end capable of being grounded; and

(ii) a lower bank conductive line comprising first and second lower bank conductive line segments separated by a lower bank conductive line gap identifying the selected memory partition boundary, the first lower bank conductive line segment having a first end capable of receiving the DC common voltage, the second lower bank conductive line segment having a second end capable of being grounded;

(b) an encoder, coupled to the memory boundary option, capable of generating a plurality of code bits of a bank selector code with values of the bits selected based upon a location of the partition of memory into an upper memory bank and a lower memory bank at the selected memory partition boundary in response to receiving the partition boundary indicator signal; and

(c) a decoder coupled to receive the bank selector code from the encoder and further coupled to receive a plurality of memory address bits of a memory address, the decoder having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.

2. The bank selector circuit of claim 1, wherein the encoder comprises a ROM array comprising a plurality of ROM cells arranged in a plurality of columns and rows.

3. The bank selector circuit of claim 2, wherein the ROM cells each have a channel width-to-length (W/L) ratio of about 2.3/0.7.

4. The bank selector circuit of claim 2, wherein the encoder further comprises a plurality of inverters arranged in a plurality of columns, each column of the inverters coupled to a respective one of the columns of the ROM cells.

5. The bank selector circuit of claim 1, wherein the partition indicator circuit comprises a plurality of partition boundary indicator terminals each coupled to a respective one of the rows of the ROM cells.

6. The bank selector circuit of claim 5, wherein the partition indicator circuit further comprises a plurality of NOR gates each having first and second inputs and an output, the first and second inputs of the NOR gates coupled to the upper and lower bank conductive lines, respectively, and the outputs of the NOR gates forming the respective partition boundary indicator terminals.

7. The bank selector circuit of claim 1, wherein the first ends of the upper and lower bank conductive line segments are positioned opposite each other, the second ends of the upper and lower bank conductive line segments are positioned opposite each other, and the upper and lower bank conductive line gaps are positioned corresponding to each other.

8. The bank selector circuit for a non-volatile memory device with a flexible bank partition architecture comprising:

(a) a memory boundary option designating a memory partition boundary selected from a plurality of predetermined memory partition boundaries, the memory boundary option capable of generating a partition boundary indicator signal based upon the selected memory partition boundary;

(b) an encoder, coupled to the memory boundary option, capable of generating a plurality of code bits of a bank selector code with values of the bits selected based upon a location of the partition of memory into an upper memory bank and a lower memory bank at the selected memory partition boundary in response to receiving the partition boundary indicator signal; and

(c) a decoder coupled to receive the bank selector code from the encoder and further coupled to receive a plurality of memory address bits of a memory address, the decoder having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank, wherein the decoder comprises;

(i) a logic bit P determining circuit coupled to receive a first plurality of the code bits and a first plurality of the memory address bits;

(ii) a logic bit Q determining circuit coupled to receive a second plurality of the code bits and the first plurality of the memory address bits; and

(iii) a logic bit O determining circuit coupled to receive a remaining one of the code bits and a second plurality of the memory address bits.

9. The bank selector circuit of claim 8, wherein the decoder further comprises an output logic circuit coupled to the logic bit O, P and Q determining circuits, the output logic circuit having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.

10. The bank selector circuit of claim 9, wherein the output logic circuit comprises:

(i) an AND gate having first and second AND gate inputs and an AND gate output, the first and second AND gate inputs connected to the logic bit P and Q determining circuits, respectively; and

(ii) a NOR gate having first and second NOR gate inputs and a NOR gate output, the first and second NOR gate inputs connected to the logic bit O determining circuit and to the AND gate output, respectively, the NOR gate output forming the bank selector output.

11. The bank selector circuit of claim 8, wherein the logic bit O, P and Q determining circuits comprise a plurality of PMOS transistors each having a channel width-to-length (W/L) ratio of about 20/0.65.

12. The bank selector circuit of claim 11, wherein the logic bit O, P and Q determining circuits further comprise a plurality of NMOS transistors each having a channel W/L ratio of about 20/0.5.

13. The bank selector circuit of claim 8, wherein the logic bit O determining circuit comprises means for determining whether the memory address belongs to a hidden sector of the memory.

14. The bank selector circuit of claim 8, wherein the logic bit O, P and Q determining circuits comprise means for determining the logic bits O, P and Q, respectively.

15. A bank selector circuit for a simultaneous operation non-volatile memory device with a flexible bank partition architecture, comprising:

(a) a bank selector encoder capable of generating a plurality of code bits of a bank selector code based upon a partition of memory into an upper memory bank and a lower memory bank at a memory partition boundary selected from a plurality of predetermined partition boundaries;

(b) a plurality of memory address inputs capable of receiving a plurality of memory address bits of a memory address;

(c) a logic bit P determining circuit coupled to receive a first plurality of the code bits and a first plurality of the memory address bits;

(d) a logic bit Q determining circuit coupled to receive a second plurality of the code bits and the first plurality of the memory address bits;

(e) a logic bit O determining circuit coupled to receive a remaining one of the code bits and a second plurality of the memory address bits; and

(f) an output logic circuit coupled to the logic bit O, P and Q determining circuits, the output logic circuit having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.

16. The bank selector circuit of claim 15, wherein the output logic circuit comprises:

(i) an AND gate having first and second AND gate inputs and an AND gate output, the first and second AND gate inputs connected to the logic bit P and Q determining circuits, respectively; and

(ii) a NOR gate having first and second NOR gate inputs and a NOR gate output, the first and second NOR gate inputs connected to the logic bit O determining circuit and to the AND gate output, respectively, the NOR gate output forming the bank selector output.

17. The bank selector circuit of claim 15, wherein the logic bit O, P and Q determining circuits comprise a plurality of PMOS transistors each having a channel width-to-length (W/L) ratio of about 20/0.65.

18. The bank selector circuit of claim 17, wherein the logic bit O, P and Q determining circuits further comprise a plurality of NMOS transistors each having a channel W/L ratio of about 20/0.5.

19. The bank selector circuit of claim 15, wherein the logic bit O determining circuit comprises means for determining whether the memory address belongs to a hidden sector of the memory.

20. The bank selector circuit of claim 15, wherein the bank selector encoder comprises a ROM array comprising a plurality of ROM cells arranged in a plurality of columns and rows.

21. The bank selector circuit of claim 20, wherein the ROM cells each have a channel width-to-length (W/L) ratio of about 2.3/0.7.

22. The bank selector circuit of claim 20, wherein the bank selector encoder further comprises a partition indicator circuit capable of designating the selected memory partition boundary that separates the memory into the upper memory bank and the lower memory bank, the partition indicator circuit comprising a plurality of partition boundary indicator terminals each coupled to a respective one of the rows of the ROM cells.

23. The bank selector circuit of claim 22, wherein the bank selector encoder further comprises a plurality of inverters arranged in a plurality of columns, each column of the inverters coupled to a respective one of the columns of the ROM cells.

24. The bank selector circuit of claim 22, wherein the partition indicator circuit further comprises:

(i) an upper bank conductive line comprising first and second upper bank conductive line segments separated by an upper bank conductive line gap designating the selected memory partition boundary, the first upper bank conductive line segment having a first end capable of receiving a DC common voltage, and the second upper bank conductive line segment having a second end capable of being grounded; and

(ii) a lower bank conductive line comprising first and second lower bank conductive line segments separated by a lower bank conductive line gap designating the selected memory partition boundary, the first lower bank conductive line segment having a first end capable of receiving the DC common voltage, the second lower bank conductive line segment having a second end capable of being grounded, the first ends of the upper and lower bank conductive line segments positioned opposite each other, the second ends of the upper and lower bank conductive line segments positioned opposite each other, and the upper and lower bank conductive line gaps positioned corresponding to each other.

25. The bank selector circuit of claim 24, wherein the partition indicator circuit further comprises a plurality of NOR gates each having first and second inputs and an output, the first and second inputs of the NOR gates coupled to the upper and lower bank conductive lines, respectively, and the outputs of the NOR gates forming the respective partition boundary indicator terminals.

26. The bank selector circuit of claim 22, wherein the partition indicator circuit comprises means for designating the partition of the memory into the upper memory bank and the lower memory bank.

27. A bank selector circuit for a simultaneous operation non-volatile memory device with a flexible bank partition architecture, comprising:

(a) a bank selector encoder, comprising;

(i) a partition indicator circuit comprising a plurality of partition boundary indicator terminals capable of designating a partition of memory into an upper memory bank and a lower memory bank at a memory partition boundary selected from a plurality of predetermined partition boundaries;

(ii) a ROM array comprising a plurality of ROM cells arranged in a plurality of columns and rows, each row of the ROM cells coupled to a respective one of the partition boundary indicator terminals;

(iii) a plurality of inverters arranged in a plurality of columns, each column of the inverters coupled to a respective one of the columns of the ROM cells; and

(iv) a plurality of bank selector code outputs, coupled to the respective columns of the inverters, capable of outputting a plurality of code bits of a bank selector code;

(b) a plurality of memory address inputs capable of receiving a plurality of memory address bits of a memory address;

(c) means for determining logic bit P, coupled to a first plurality of the bank selector code outputs and to a first plurality of the memory address inputs;

(d) means for determining logic bit Q, coupled to a second plurality of the bank selector code outputs and to the first plurality of the memory address inputs;

(e) means for determining logic bit O, coupled to a remaining one of the bank selector code outputs and to a second plurality of the memory address inputs; and

(f) an output logic circuit coupled to the means for determining the logic bits O, P and Q, the output logic circuit having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.

28. The bank selector circuit of claim 27, wherein the output logic circuit comprises:

(i) an AND gate having first and second AND gate inputs and an AND gate output, the first and second AND gate inputs connected to the means for determining the logic bits P and Q, respectively; and

(ii) a NOR gate having first and second NOR gate inputs and a NOR gate output, the first and second NOR gate inputs connected to the means for determining the logic bit O and to the AND gate output, respectively, the NOR gate output forming the bank selector output.

29. The bank selector circuit of claim 27, wherein the means for determining the logic bits O, P and Q comprise a plurality of PMOS transistors each having a channel width-to-length (W/L) ratio of about 20/0.65.

30. The bank selector circuit of claim 29, wherein the means for determining the logic bits O, P and Q further comprise a plurality of NMOS transistors each having a channel W/L ratio of about b 20/0.5.

31. The bank selector circuit of claim 27, wherein the means for determining the logic bit O comprises means for determining whether the memory address belongs to a hidden sector of the memory.

32. The bank selector circuit of claim 27, wherein the ROM cells in the bank selector encoder each have a channel width-to-length (W/L) ratio of about 2.3/0.7.

33. The bank selector circuit of claim 27, wherein the partition indicator circuit further comprises:

(i) an upper bank conductive line comprising first and second upper bank conductive line segments separated by an upper bank conductive line gap designating the selected memory partition boundary, the first upper bank conductive line segment having a first end capable of receiving a DC common voltage, and the second upper bank conductive line segment having a second end capable of being grounded; and

(ii) a lower bank conductive line comprising first and second lower bank conductive line segments separated by a lower bank conductive line gap designating the selected memory partition boundary, the first lower bank conductive line segment having a first end capable of receiving the DC common voltage, the second lower bank conductive line segment having a second end capable of being grounded, the first ends of the upper and lower bank conductive line segments positioned opposite each other, the second ends of the upper and lower bank conductive line segments positioned opposite each other, and the upper and lower bank conductive line gaps positioned corresponding to each other.

34. The bank selector circuit of claim 33, wherein the partition indicator circuit further comprises a plurality of NOR gates each having first and second inputs and an output, the first and second inputs of the NOR gates coupled to the upper and lower bank conductive lines, respectively, and the outputs of the NOR gates forming the respective partition boundary indicator terminals.

35. The bank selector circuit of claim 27, wherein the partition indicator circuit comprises means for designating the partition of the memory into the upper memory bank and the lower memory bank.

36. The bank selector circuit of claim 27, wherein the bank selector encoder comprises means for generating the code bits of the bank selector code.

37. A bank selector circuit for a simultaneous operation non-volatile memory device with a flexible bank partition architecture, comprising:

(a) means for generating a plurality of code bits of a bank selector code based upon a partition of memory into an upper memory bank and a lower memory bank at a memory partition boundary selected from a plurality of predetermined partition boundaries;

(b) a plurality of memory address inputs capable of receiving a plurality of memory address bits of a memory address;

(c) means for determining logic bit P, coupled to the means for generating the code bits of the bank selector code and to a first plurality of the memory address inputs;

(d) means for determining logic bit Q, coupled to the means for generating the code bits of the bank selector code and to the first plurality of the memory address inputs;

(e) means for determining logic bit O, coupled to the means for generating the code bits of the bank selector code and to a second plurality of the memory address inputs; and

(f) an output logic circuit coupled to the means for determining the logic bits O, P and Q, the output logic circuit having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.

38. The bank selector circuit of claim 37, wherein the output logic circuit comprises:

(i) an AND gate having first and second AND gate inputs and an AND gate output, the first and second AND gate inputs connected to the means for determining the logic bits P and Q, respectively; and

(ii) a NOR gate having first and second NOR gate inputs and a NOR gate output, the first and second NOR gate inputs connected to the means for determining the logic bit O and to the AND gate output, respectively, the NOR gate output forming the bank selector output.

39. The bank selector circuit of claim 37, wherein the means for determining the logic bits O, P and Q comprise a plurality of PMOS transistors each having a channel width-to-length (W/L) ratio of about 20/0.65.

40. The bank selector circuit of claim 39, wherein the means for determining the logic bits O, P and Q further comprise a plurality of NMOS transistors each having a channel W/L ratio of about 20/0.5.

41. The bank selector circuit of claim 37, wherein the means for determining the logic bit O comprises means for determining whether the memory address belongs to a hidden sector of the memory.

42. The bank selector circuit of claim 37, wherein the means for generating the code bits of the bank selector code comprises a ROM array comprising a plurality of ROM cells arranged in a plurality of columns and rows.

43. The bank selector circuit of claim 42, wherein the ROM cells each have a channel width-to-length (W/L) ratio of about 2.3/0.7.

44. The bank selector circuit of claim 42, wherein the means for generating the code bits of the bank selector code further comprises a partition indicator circuit capable of designating the selected memory partition boundary that separates the memory into the upper memory bank and the lower memory bank, the partition indicator circuit comprising a plurality of partition boundary indicator terminals each coupled to a respective one of the rows of the ROM cells.

45. The bank selector circuit of claim 44, wherein the means for generating the code bits of the bank selector code further comprises a plurality of inverters arranged in a plurality of columns, each column of the inverters coupled to a respective one of the columns of the ROM cells.

46. The bank selector circuit of claim 44, wherein the partition indicator circuit further comprises:

(i) an upper bank conductive line comprising first and second upper bank conductive line segments separated by an upper bank conductive line gap designating the selected memory partition boundary, the first upper bank conductive line segment having a first end capable of receiving a DC common voltage, and the second upper bank conductive line segment having a second end capable of being grounded; and

(ii) a lower bank conductive line comprising first and second lower bank conductive line segments separated by a lower bank conductive line gap designating the selected memory partition boundary, the first lower bank conductive line segment having a first end capable of receiving the DC common voltage, the second lower bank conductive line segment having a second end capable of being grounded, the first ends of the upper and lower bank conductive line segments positioned opposite each other, the second ends of the upper and lower bank conductive line segments positioned opposite each other, and the upper and lower bank conductive line gaps positioned corresponding to each other.

47. The bank selector circuit of claim 46, wherein the partition indicator circuit further comprises a plurality of NOR gates each having first and second inputs and an output, the first and second inputs of the NOR gates coupled to the upper and lower bank conductive lines, respectively, and the outputs of the NOR gates forming the respective partition boundary indicator terminals.

48. The bank selector circuit of claim 44, wherein the partition indicator circuit comprises means for designating the partition of the memory into the upper memory bank and the lower memory bank.

49. A bank selector circuit for assigning a memory address to either an upper memory bank or a lower memory bank in a simultaneous operation non-volatile memory device with a flexible bank partition architecture, comprising:

(a) means for determining logic bit P in response to receiving a first plurality of memory address inputs and a first plurality of code bits of a bank selector code;

(b) means for determining logic bit Q in response to receiving the first plurality of the memory address inputs and a second plurality of the code bits of the bank selector code;

(c) means for determining logic bit O in response to receiving a second plurality of the memory address inputs and a third one of the code bits of the bank selector code; and

(d) an output logic circuit coupled to the means for determining the logic bits O, P and Q, the output logic circuit having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.

50. The bank selector circuit of claim 49, wherein the output logic circuit comprises:

(i) an AND gate having first and second AND gate inputs and an AND gate output, the first and second AND gate inputs connected to the means for determining the logic bits P and Q, respectively; and

(ii) a NOR gate having first and second NOR gate inputs and a NOR gate output, the first and second NOR gate inputs connected to the means for determining the logic bit O and to the AND gate output, respectively, the NOR gate output forming the bank selector output.

51. The bank selector circuit of claim 49, wherein the means for determining the logic bits O, P and Q comprise a plurality of PMOS transistors each having a channel width-to-length (W/L) ratio of about 20/0.65.

52. The bank selector circuit of claim 51, wherein the means for determining the logic bits O, P and Q further comprise a plurality of NMOS transistors each having a channel W/L ratio of about 20/0.5.

53. The bank selector circuit of claim 49, wherein the means for determining the logic bit O comprises means for determining whether the memory address belongs to a hidden sector of the memory.