Power controller for a peripheral device that stores the on/off state thereof when power is removed from the device

• US 6,275,949 B1
• Filed: 03/15/1999
• Issued: 08/14/2001
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: HTC Corporation
• Original Assignee: NEC Corporation
• Inventors: Watanabe, Yoshinori
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US09/267,677
• Time in Patent Office: 883 Days
• Field of Search: 713/300-340, 710/260, 710/267
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

After an activation of the CPU in a peripheral device in a computer system, a determination is made whether an external power supply input or operation of a software switch is inputted as a trigger. Based on this determination, the peripheral device is left ON or turned OFF so as to be in the same state as when power was last removed. When it is not necessary to supply the power to the peripheral device, the power to the CPU is turned OFF to reduce power consumption.

Claims

1. A power controller for a peripheral device in a computer system, the power controller comprising:

a peripheral device nonvolatile memory storing data indicating an ON/OFF state of the peripheral device when power was last removed from the computer system;

a peripheral device power supply; and

a peripheral device processor connected to said peripheral device power supply and to said peripheral device nonvolatile memory, said peripheral device processor sending an ON control signal upon receipt of a trigger signal, said ON control signal being sent to said peripheral device power supply to temporarily supply power to said peripheral device processor, said peripheral device processor further determining whether said peripheral device nonvolatile memory indicates that the peripheral device was in an ON state or an OFF state when power was last removed from the computer system and, based upon this determination, either instructing said peripheral device power supply to continuously provide power to said peripheral device processor when the peripheral device was in an ON state or sending an OFF control signal to turn off said peripheral device processor when the peripheral device was in an OFF state.

2. The power controller of claim 1, wherein said trigger signal is one of an indication that power is available to the peripheral device and an indication that an ON state has been selected.

3. The power controller of claim 2, wherein said peripheral device processor rewrites the data indicating an ON/OFF state of the peripheral device when power was last removed from the computer system based on said trigger signal.