Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes

• US 6,277,698 B1
• Filed: 08/25/1999
• Issued: 08/21/2001
• Est. Priority Date: 08/25/1999
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ishida, Emi, Ju, Dong-Hyuk, Wu, David
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/382,580
• Time in Patent Office: 727 Days
• Field of Search: 438/626, 438/239, 438/253, 438/254, 438/381, 438/396, 438/397, 438/230, 438/299, 438/301, 438/162, 438/585, 438/592, 438/659, 438/180, 438/229
• US Class Current: 438/299
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

Claims

1. A method of manufacturing a semiconductor device, which method comprises:

forming a first dielectric layer, comprising a first dielectric material, on an upper surface of a semiconductor substrate;

forming a second dielectric layer, comprising a second dielectric material different from the first dielectric material, directly on the first dielectric layer;

patterning and etching the second dielectric layer to form regions having a rectangular profile on the first dielectric layer, separated by open regions;

depositing a layer of gate electrode material on the semiconductor substrate filling the open regions; and

planarizing the layer of gate electrode material leaving gate electrode material in the open regions having an upper surface and side surfaces, wherein the side surfaces are substantially parallel to each other and substantially perpendicular to the upper surface of the semiconductor substrate.

2. The method of claim 1, comprising:

implanting impurities into the gate electrode material filling the openings.

3. The method of claim 2, comprising:

activation annealing at a temperature of about 900°

C. to about 1075°

C. to activate the impurities forming a gate electrode.

4. The method of claim 3, comprising:

removing the second dielectric layer by etching.

5. The method of claim 4, comprising:

ion implanting impurities, using the gate electrode as a mask, to form source/drain extension implants in the semiconductor substrate;

depositing an insulating layer on the semiconductor substrate; and

etching the insulating layer to form insulating sidewall spacers on the side surfaces of the gate electrode.

6. The method of claim 5, comprising:

ion implanting impurities, using the gate electrode and sidewall spacers as a mask, to form moderately or heavily doped implants in the semiconductor substrate; and

activation annealing the implanted impurities to form source/drain regions in the semiconductor substrate.

7. The method of claim 1, wherein the second dielectric layer comprises a stacked structure with a first dielectric sub-layer formed on the first dielectric layer and a second dielectric sub-layer formed on the first dielectric sub-layer.

8. The method of claim 7, wherein the first dielectric layer comprises a silicon oxide and the first dielectric sub-layer comprises a silicon nitride.

9. The method of claim 1, wherein the planarizing step comprises chemical-mechanical polishing.

10. A method of manufacturing a CMOS semiconductor device having an N-channel transistor region and a P-channel transistor region, which method comprises:

forming a first dielectric layer, comprising a first dielectric material, on an upper surface of a semiconductor substrate;

forming a second dielectric layer, comprising a second dielectric material different from the first dielectric material, directly on the first dielectric layer;

patterning and etching the second dielectric layer to form regions having a rectangular profile on the first dielectric layer, separated by open regions;

depositing a layer comprising a gate electrode material on the semiconductor substrate filling the open regions; and

planarizing the layer comprising a gate electrode material leaving gate electrode material in the openings in a N-channel transistor and P-channel transistor regions having an upper surface and side surfaces, wherein the side surfaces are substantially parallel to each other and substantially perpendicular to the upper surface of the semiconductor substrate.

11. The method of claim 10, comprising:

forming a mask over the P-channel transistor region;

implanting N-type impurities to dope the gate electrode material in the N-channel transistor region;

removing the P-channel transistor region mask; and

activation annealing to activate the N-type impurities forming a first gate electrode.

12. The method of claim 11, comprising:

forming a mask over the N-channel transistor region;

implanting P-type impurities to dope the gate electrode material in the P-channel transistor region;

removing the N-channel transistor region mask; and

activation annealing to activate the P-type impurities forming a second gate electrode.

13. The method of claim 12, comprising removing the second dielectric layer by etching;

implanting N-type impurities, using the first gate electrode as a mask, to form N-type source/drain extension implants of the N-channel transistor;

depositing an insulating layer on the semiconductor substrate;

etching the insulating layer to form insulating sidewall spacers on the side surfaces of the first and second gate electrodes;

implanting N-type impurities, using the first gate electrode and insulating sidewall spacers as a mask, to form N-type moderately doped or heavily doped implants of the N-channel transistor;

implanting P-type impurities, using the second gate electrode and insulating sidewall spacers as a mask, to form P-type source/drain implants of the P-channel transistor; and

activation annealing to form source/drain regions of the N-channel transistor and the P-channel transistor.

14. The method of claim 10, wherein the gate electrode material comprises polycrystalline silicon and the second dielectric layer comprises a silicon nitride.

15. The method of claim 10, wherein the second dielectric layer comprises a stacked structure with a first dielectric sub-layer formed on the first dielectric layer and a second dielectric sub-layer formed on the first dielectric sub-layer.

16. The method of claim 10, comprising:

removing the second dielectric layer;

implanting impurities to dope the first gate electrode; and

implanting impurities to dope the second gate electrode.

17. The method of claim 16, comprising:

implanting impurities to form source/drain implants of the N-channel transistor;

implanting impurities to form source/drain implants of the P-channel transistor; and

activation annealing to form source/drain regions of the N-channel transistor and the P-channel transistor.

18. A method of manufacturing a semiconductor device, the method comprising sequentially:

forming a first dielectric layer on an upper surface of a semiconductor substrate;

forming a film on the first dielectric layer;

patterning the film to form regions, separated by openings, having a rectangular profile on the first dielectric layer;

depositing a layer of gate electrode material filling the openings with gate electrode material;

planarizing the layer of gate electrode material leaving gate electrode material in the openings having an upper surface and substantially parallel side surfaces substantially perpendicular to the upper surface of the semiconductor substrate;

ion implanting impurities into the gate electrode material filling the openings;

removing the film; and

ion implanting to form source/drain regions.

19. The method of claim 18, wherein the first dielectric layer comprises a dielectric material and the film comprises a second dielectric different from the first dielectric material.

20. The method of claim 19, wherein the first dielectric layer comprises silicon oxide and the second dielectric material comprises silicon nitride.