Method of manufacturing semiconductor device having a recessed gate structure

• US 6,277,707 B1
• Filed: 12/16/1998
• Issued: 08/21/2001
• Est. Priority Date: 12/16/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Taravade, Kunal N., Miller, Gayle W., Lee, Brian R.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/212,931
• Time in Patent Office: 979 Days
• Field of Search: 438/268, 438/270, 438/272, 438/294, 438/296, 438/334, 438/424, 438/430, 438/689, 438/959
• US Class Current: 438/430
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A method of forming a semiconductor device on a substrate including the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

Claims

1. A method of forming a semiconductor device on a substrate, comprising the steps of:

forming a first recess in the substrate;

depositing an insulator on the substrate and in the first recess so that an isolation region is formed when the first recess is filled with the insulator;

forming a second recess in a predetermined area of the substrate by removing a portion of the substrate in the predetermined area and a portion of the insulator disposed over the predetermined area;

forming a recess insulation layer on the surface of the substrate and in the second recess;

depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material;

removing a sufficient amount of the insulator, the recess insulation layer and the conductive material so that top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

2. A method according to claim 1 wherein the step of forming the first recess comprises:

etching the substrate with a plasma of etchant gas.

3. A method according to claim 2 wherein the plasma of etchant gas comprises Cl₂, CHF₃, CF₄, HBr or Ar.

4. A method according to claim 1 wherein the step of forming the second recess comprises:

etching the predetermined area of the substrate with a plasma of etchant gas.

5. A method according to claim 4 wherein the plasma of etchant gas comprises Cl₂, CHF₃, CF₄, HBr or Ar.

6. A method according to claim 1 wherein the step of depositing the conductive material is performed by chemical vapor deposition.

7. A method according to claim 1 wherein the step of removing the sufficient amount of the insulator and the conductive material comprises the steps of:

etching the insulator and the conductive material with a plasma of etchant gas;

and

planarizing the top surface of the insulator and the top surface of the conductive material.

8. A method according to claim 7 wherein the plasma of etchant gas comprises Cl₂, CHF₃, CF₄, HBr or Ar.

9. A method according to claim 1 wherein the step of removing comprises:

performing chemical mechanical polishing on the top surface of the insulator and the top surface of the conductive material.

10. A method according to claim 9 wherein the top surface of the insulator and the top surface of the conductive material are polished concurrently.

11. A method according to claim 1 wherein the recess insulation layer comprises TEOS.

12. A method according to claim 1 further comprising:

doping the gate region and at least one source/drain region near the gate region after the removing step.

13. A method according to claim 12 further comprising:

forming a contact on the source/drain region after the doping step.

14. A method of forming a semiconductor device on a substrate having a top surface, comprising the steps of:

forming an isolation region containing an insulator in the substrate and a recessed conductor insulated from and disposed within the substrate, said step of forming leaving residual materials disposed above said substrate;

removing said residual materials so that said insulator and said conductor are substantially aligned with the top surface of the substrate;

wherein said step of forming an isolation region includes the steps of;

forming a protective layer on the top surface of the substrate;

forming a first recess in a first predetermined region of the substrate including removing the protective layer above the first predetermined region of the substrate;

forming the isolation region insulator above the protective layer and in the first recess so that a top portion of the isolation region insulator is formed at least up to a level aligned with the top surface of the substrate;

forming a second recess in a second predetermined region of the substrate including removing the protective layer and the isolation region insulator above the second predetermined region of the substrate;

forming a recess insulation layer above the insulator and on the surface of the second recess;

forming a conductive material on the recess insulation layer and in the second recess so that a top portion of the conductive material is formed at least up to a level aligned with the top surface of the substrate; and

wherein the step of removing removes a sufficient amount of the isolation region insulator, the recess insulation layer and the conductive material so that their remains a top surface of the insulator and a top surface of the conductive material that are substantially aligned with the top surface of the substrate.

15. A method according to claim 14 wherein the step of forming the first recess comprises:

etching the substrate and the protective layer with a plasma of etchant gas.

16. A method according to claim 15 wherein the plasma of etchant gas comprises Cl₂, CHF₃, CF₄, HBr or Ar.

17. A method according to claim 14 wherein the step of forming the second recess comprises:

etching the substrate, the protective layer and the insulator with a plasma of etchant gas.

18. A method according to claim 17 wherein the plasma of etchant gas comprises.

19. A method according to claim 14 wherein the step of removing the sufficient amount of the insulator and the conductive material comprises the steps of:

etching the insulator and the conductive material with a plasma of etchant gas;

and

planarizing the top surface of the insulator and the top surface of the conductive material.

20. A method according to claim 19 wherein the plasma of etchant gas comprises Cl₂, CHF₃, CF₄, HBr or Ar.

21. A method according to claim 20 wherein step of planarizing comprises:

performing chemical mechanical polishing on the top surfaces of the insulator and the conductive material.

22. A method according to claim 14 further comprising:

doping the conductive material in the second recess and a predetermined region in the substrate near the second recess after the step of planarizing.

23. A method according to claim 14 further comprising:

removing the protective layer after the step of planarizing.

24. A method of forming an electrical device on an active area of a substrate having a top surface, the active area being within an isolation region in the substrate, the isolation region containing an insulator disposed over the substrate, the method comprising the steps of:

etching a trench in a predetermined area in the substrate within the isolation region to remove a portion of the substrate and a portion of the insulator disposed over the predetermined area of the substrate;

forming an insulating layer on the surface of the substrate and in the trench;

forming a conductive layer on top of the insulating layer and in the trench so that a top portion of the conductive layer is formed at least up to a level aligned with the top surface of the substrate; and

removing a sufficient amount of the insulator, the insulating layer and the conductive layer so that the top surface of the conductive layer is at a level that is substantially aligned with the top surface of the substrate and the isolation region.

25. A method according to claim 24 wherein the step of etching the trench comprises:

using a plasma of Cl2 or HBr gas to etch the trench.

26. A method according to claim 24 wherein the step of removing the sufficient amount of the insulator and the conductive layer comprises the steps of:

etching the insulator and the conductive layer with a plasma of etchant gas; and

planarizing the top surface of the insulator and the top surface of the conductive layer.

27. A method according to claim 26 wherein the plasma of etchant gas comprises Cl₂, CHF₃, CF₄, HBr or Ar.

28. A method according to claim 26 wherein the step of planarizing comprises:

performing chemical mechanical polishing on the top surfaces of the insulator and the conductive layer.