Semiconductor device and method of manufacturing the same

• US 6,278,132 B1
• Filed: 03/18/1999
• Issued: 08/21/2001
• Est. Priority Date: 07/11/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fukunaga, Takeshi, Ohtani, Hisashi, Yamazaki, Shunpei
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US09/272,701
• Time in Patent Office: 887 Days
• Field of Search: 257/65, 257/66, 257/69, 257/72, 257/347, 257/351, 257/352, 438/149, 438/154
• US Class Current: 257/69
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.

Claims

1. A liquid crystal display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

2. A liquid crystal display device according to claim 1 wherein said S value is 75 mV/dec or lower.

3. A liquid crystal display device according to claim 1 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

4. A liquid crystal display device according to claim 1 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

5. A liquid crystal display device according to claim 1 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

6. An electroluminescent display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

7. An electroluminescent display device according to claim 6 wherein said S value is 75 mV/dec or lower.

8. An electroluminescent display device according to claim 6 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

9. An electroluminescent display device according to claim 6 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

10. An electroluminescent display device according to claim 6 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

11. A TV camera comprising a main body, a camera, a liquid crystal display device and operation switches, said liquid crystal display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

12. A TV camera according to claim 11 wherein said S value is 75 mV/dec or lower.

13. A TV camera according to claim 11 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

14. A TV camera according to claim 11 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

15. A TV camera according to claim 11 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

16. A TV camera comprising a main body, a camera, an electroluminescent display device and operation switches, said electroluminescent display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

17. A TV camera according to claim 16 wherein said S value is 75 mV/dec or lower.

18. A TV camera according to claim 16 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

19. A TV camera according to claim 16 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

20. A TV camera according to claim 16 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

21. A personal computer comprising a main body, a cover portion, a keyboard and a liquid crystal display device, said liquid crystal display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

22. A personal computer according to claim 21 wherein said S value is 75 mV/dec or lower.

23. A personal computer according to claim 21 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

24. A personal computer according to claim 21 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

25. A personal computer according to claim 21 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

26. A personal computer comprising a main body, a cover portion, a keyboard and an electroluminescent display device, said electroluminescent display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

27. A personal computer according to claim 26 wherein said S value is 75 mV/dec or lower.

28. A personal computer according to claim 26 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

29. A personal computer according to claim 26 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

30. A personal computer according to claim 26 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

31. A TV projection system comprising a main body, a light source, a liquid crystal display device, a mirror and a screen, said liquid crystal display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

32. A TV projection system according to claim 31 wherein said S value is 75 mV/dec or lower.

33. A TV projection system according to claim 31 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

34. A TV projection system according to claim 31 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

35. A TV projection system according to claim 31 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

36. A TV projection system comprising a main body, a light source, an electroluminescent display device, a mirror and a screen, said electroluminescent display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

37. A TV projection system according to claim 36 wherein said S value is 75 mV/dec or lower.

38. A TV projection system according to claim 36 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

39. A TV projection system according to claim 36 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

40. A TV projection system according to claim 36 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

41. A video camera comprising a main body, a liquid crystal display device, an eye piece, operation switches and a tape holder, said liquid crystal display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

42. A video camera according to claim 41 wherein said S value is 75 mV/dec or lower.

43. A video camera according to claim 41 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

44. A video camera according to claim 41 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

45. A video camera according to claim 41 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

46. A video camera comprising a main body, an electroluminescent display device, an eye piece, operation switches and a tape holder, said electroluminescent display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

47. A video camera according to claim 46 wherein said S value is 75 mV/dec or lower.

48. A video camera according to claim 46 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

49. A video camera according to claim 46 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

50. A video camera according to claim 46 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

51. A car navigation system comprising a main body, a liquid crystal display device, operation switches and an antenna, said liquid crystal display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

52. A car navigation system according to claim 51 wherein said S value is 75 mV/dec or lower.

53. A car navigation system according to claim 51 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

54. A car navigation system according to claim 51 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

55. A car navigation system according to claim 51 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.

56. A car navigation system comprising a main body, an electroluminescent display device, operation switches and antenna, said electroluminescent display device comprising:

a substrate;

an underlying film formed on said substrate;

a shift register circuit comprising a plurality of clocked inverter circuits and a plurality of inverter circuits provided over said substrate, each of said clocked inverter circuits and said inverter circuits comprising at least one n-channel thin film transistor exhibiting normally OFF characteristics and at least one p-channel thin film transistor exhibiting normally OFF characteristics;

said n-channel thin film transistor comprising a first crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

;

said p-channel thin film transistor comprising a second crystalline semiconductor film comprising silicon having a thickness of 100 to 1,000 Å

,

wherein at least an edge portion of said first crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and at least a channel region of said second crystalline semiconductor film comprises boron introduced at a concentration of 1×

10¹⁶ to 1×

10¹⁹/cm³, and

wherein said shift register has an S value of 85 mV/dec or lower.

57. A video camera according to claim 56 wherein said S value is 75 mV/dec or lower.

58. A video camera according to claim 56 wherein said substrate is selected from a glass substrate, a quartz substrate and a silicon substrate.

59. A video camera according to claim 56 wherein a difference between a threshold voltage of said n-channel thin film transistor and that of said p-channel thin film transistor is within a range of 0.2 to 1V.

60. A video camera according to claim 56 wherein one of said clocked inverter circuit comprises two n-channel thin film transistors and two p-channel thin film transistors connected serially.