Insulated gate thyristor

• US 6,278,140 B1
• Filed: 02/24/2000
• Issued: 08/21/2001
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Iwamuro, Noriyuki, Harada, Yuichi, Iwaana, Tadayoshi
• Primary Examiner(s): Ngô , Ngân V.
• Application Number:
  US09/511,167
• Time in Patent Office: 544 Days
• Field of Search: 257/133, 257/137, 257/138, 257/152, 257/168, 257/169
• US Class Current: 257/133
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. The thyristor further includes a first main electrode that contacts with both the first base region and the first-conductivity-type source region, a second-conductivity-type emitter layer formed on the other surface of the first-conductivity-type base layer, a second main electrode that contacts with the second-conductivity-type emitter layer, a gate electrode connected to the gate electrode layer; and an insulating film covering entire surface areas of the second second-conductivity-type base region and the first-conductivity-type emitter region. In this insulated gate thyristor, an exposed surface portion of the first second-conductivity-type base region that is interposed between the first-conductivity-type base layer and the first-conductivity-type source region has a smaller width than an exposed surface portion of the second second-conductivity-type base region interposed between the first-conductivity-type base layer and the first-conductivity-type emitter region.

Claims

1. An insulated gate thyristor comprising:

a first-conductivity-type base layer having a high resistivity;

first and second-conductivity-type base regions formed in selected portions of a surface layer of said first-conductivity-type base layer at a first major surface thereof;

a first-conductivity-type source region formed in a selected portion of a surface layer of said first second-conductivity-type base region;

a first-conductivity-type emitter region formed in a selected portion of a surface layer of said second second-conductivity-type base region;

a gate electrode layer formed on a gate insulating film over a surface of said first second-conductivity-type base region, an exposed portion of said first-conductivity-type base layer, and a surface of said second second-conductivity-type base region, which surfaces and exposed portions are interposed between said first-conductivity-type source region and said first-conductivity-type emitter region;

a first main electrode that contacts with both an exposed portion of said first second-conductivity-type base region and said first-conductivity-type source region;

a second-conductivity-type emitter layer formed on a second major surface of said first-conductivity-type base layer;

a second main electrode that contacts with said second-conductivity-type emitter layer;

a gate electrode that contacts with said gate electrode layer; and

an insulating film covering entire areas of surfaces of said second second-conductivity-type base region and said first-conductivity-type emitter region,

wherein said first-second conductivity-type base region has a lower impurity concentration than said second second-conductivity-type base region.

2. An insulated gate thyristor as claimed in claim 1, wherein said first-conductivity-type base layer comprises an epitaxial wafer including a first-conductivity-type buffer layer located between the first-conductivity-type epitaxial base layer and the second-conductivity-type emitter layer.

3. An insulated gate thyristor as claimed in claim 1, wherein said first-conductivity-type base layer comprises a bulk wafer.