Integrated device package and fabrication methods thereof

• US 6,278,178 B1
• Filed: 01/26/1999
• Issued: 08/21/2001
• Est. Priority Date: 02/10/1998
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Jin Sung, Kwon, Yong Tae
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US09/237,228
• Time in Patent Office: 938 Days
• Field of Search: 257/684, 257/692, 257/700, 257/690, 257/668, 257/697, 257/698, 257/778, 438/108
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Claims

1. A substrate for an integrated package, comprising:

an insulating substrate;

a plurality of conductive first lands formed on a first surface of the insulating substrate;

a plurality of conductive second lands formed on a second surface of the insulating substrate;

a plurality of via holes formed in the insulating substrate adjacent the first lands and the second lands;

a plurality of conductive media formed in the via holes and electrically connecting corresponding ones of the first lands and the second lands; and

at least one central cavity formed in a central portion of the substrate, wherein an edge of the at least one central cavity extends through a row of via holes; and

at least one peripheral cavity formed adjacent a peripheral edge of the substrate, wherein an edge of the at least one peripheral cavity extends through a row of via holes.

2. The substrate of claim 1, wherein the first surface of the insulating substrate is opposite the second surface of the insulating substrate.

3. The substrate of claim 1, wherein said at least one peripheral cavity comprises a first peripheral cavity formed adjacent a first edge of the insulating substrate, and a second peripheral cavity formed adjacent a second edge of the insulating substrate.

4. The substrate of claim 1, wherein an edge of the at least one central cavity extends substantially along a center line of a row of via holes.

5. The substrate of claim 1, wherein the plurality of via holes comprise:

a first plurality of via holes located in a central portion of the substrate and arranged along the at least one central cavity; and

a second plurality of via holes located adjacent an edge of the substrate and arranged along the at least one peripheral cavity.

6. The substrate of claim 1, wherein the via holes comprise cylindrical surfaces that extend between the first and second surfaces of the substrate, and wherein the plurality of conductive media formed in the via holes are located on the cylindrical surfaces of the via holes.

7. The substrate of claim 1, wherein the plurality of conductive first lands on the first surface of the insulating substrate comprise:

a first plurality of conductive first lands that extend from the at least one central cavity toward a peripheral edge of the substrate; and

a second plurality of conductive first lands that extend from the at least one peripheral cavity toward a central portion of the substrate.

8. The substrate of claim 7, wherein the first plurality of first conductive lands is interleaved with the second plurality of first conductive lands.

9. An integrated package, comprising:

a) a substrate having;

an insulating substrate,

a plurality of conductive first lands formed on a first surface of the insulating substrate,

a plurality of conductive second lands formed on a second surface of the insulating substrate,

a plurality of via holes formed in the insulating substrate adjacent the first lands and the second lands,

a plurality of first conductive media formed on inner walls of the via holes and electrically connecting corresponding ones of the first lands and the second lands,

at least one central cavity located in a central portion of the substrate and having an edge that extends substantially through a row of the via holes, and

at least one peripheral cavity located adjacent a peripheral edge of the substrate and having an edge that extends through a row of via holes;

b) an integrated circuit having a plurality of bond pads, wherein the integrated circuit is attached to the first surface of the substrate;

c) a plurality of second conductive media for connecting corresponding ones of the bond pads and the first lands; and

d) an insulation resin packaging the integrated circuit, the plurality of second conductive media, and the first lands.

10. The package of claim 9, wherein the plurality of second conductive media comprise at least one of wires, solder balls and solder bumps.

11. The package of claim 9, wherein the plurality of first conductive media comprise a conductive film formed on inner walls of the via holes.

12. The package of claim 9, wherein edges of the at least one central cavity and the at least one peripheral cavity each extend substantially along a centerline of a row of via holes.

13. The package of claim 9, wherein the plurality of via holes comprise:

a first plurality of via holes located in a central portion of the substrate and arranged along the at least one central cavity; and

a second plurality of via holes located adjacent a peripheral edge of the substrate and arranged along the at least one peripheral cavity.

14. The package of claim 9, wherein the via holes comprise cylindrical surfaces that extend between the first and second surfaces of the substrate, and wherein the plurality of first conductive media are formed on the cylindrical surfaces of the via holes.

15. The package of claim 9, wherein the plurality of conductive first lands comprise:

a first plurality of conductive first lands that extend from the at least one central cavity toward a peripheral edge of the substrate; and

a second plurality of conductive first lands that extend from the at least one peripheral cavity toward a central portion of the substrate.

16. The package of claim 15, wherein the first plurality of first conductive lands is interleaved with the second plurality of first conductive lands.

17. A substrate for an integrated package, comprising:

an insulating substrate;

a first plurality of conductive lands formed on a first surface of the insulating substrate;

a second plurality of conductive lands formed on the first surface of the insulating substrate1 wherein the second plurality of conductive lands are interleaved with the first plurality of conductive lands;

a third plurality of conductive lands formed on a second surface of the insulating substrate;

a plurality of via holes formed in the insulating substrate adjacent the first and second plurality of lands;

a plurality of conductive media formed in the via holes and electrically connecting each of the first and second plurality of conductive lands to corresponding ones of the third plurality of conductive lands; and

at least one cavity formed in the substrate, wherein an edge of the at least one cavity extends through a row of via holes.

18. The substrate of claim 17, wherein the at least one cavity comprises:

at least one central cavity formed in a central portion of the substrate; and

at least one peripheral cavity formed adjacent a peripheral edge of the substrate.

19. The substrate of claim 18, wherein the first plurality of conductive lands extend from the at least one central cavity toward a peripheral edge of the substrate, and wherein the second plurality of conductive lands extend from the at least one peripheral cavity toward a central portion of the substrate.

20. The substrate of claim 18, wherein the plurality of via holes comprise:

a first plurality of via holes arranged along one edge of the at least one central cavity; and

a second plurality of via holes arranged along one edge of the at least one peripheral cavity.

21. The substrate of claim 17, wherein the plurality of via holes comprise cylindrical surfaces passing between the first and second surfaces of the substrate, and wherein the plurality of conductive media are located on the cylindrical surfaces.

22. An integrated package, comprising:

a) a substrate having;

an insulating substrate,

a first plurality of conductive lands formed on a first surface of the insulating substrate,

a second plurality of conductive lands formed on the first surface of the insulating substrate, wherein the second plurality of conductive lands are interleaved with the first plurality of conductive lands,

a third plurality of conductive lands formed on a second surface of the insulating substrate,

a plurality of via holes formed in the insulating substrate adjacent the first lands and second plurality of lands,

a plurality of first conductive media formed in the via holes and electrically connecting each of the first and second plurality of conductive lands to corresponding ones of the third plurality of conductive lands, and

at least one cavity formed in the substrate, wherein an edge of the at least one cavity extends through a row of via holes;

b) an integrated circuit having a plurality of bond pads, wherein the integrated circuit is attached to the first surface of the substrate;

c) a plurality of second conductive media for connecting the bond pads to corresponding ones of the first and second plurality of conductive lands; and

d) an insulation resin packaging the integrated circuit, the plurality of second conductive media, and the first and second plurality of conductive lands.

23. The package of claim 22, wherein the at least one cavity comprises:

at least one central cavity formed in a central portion of the substrate; and

at least one peripheral cavity formed adjacent a peripheral edge of the substrate.

24. The package of claim 23, wherein the first plurality of conductive lands extend from the at least one central cavity toward a peripheral edge of the substrate, and wherein the second plurality of conductive lands extend from the at least one peripheral cavity toward a central portion of the substrate.

25. The package of claim 22, wherein the plurality of via holes comprise:

a first plurality of via holes arranged along one edge of the at least one central cavity; and

a second plurality of via holes arranged along one edge of the at least one peripheral cavity.

26. The substrate of claim 22, wherein the plurality of via holes comprise cylindrical surfaces passing between the first and second surfaces of the substrate, and wherein the plurality of first conductive media are located on the cylindrical surfaces.