Isolated well transistor structure for mitigation of single event upsets

• US 6,278,287 B1
• Filed: 10/27/1999
• Issued: 08/21/2001
• Est. Priority Date: 10/27/1999
• Status: Expired due to Term

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Baze, Mark P.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/428,239
• Time in Patent Office: 664 Days
• Field of Search: 326/9, 326/13, 326/27, 257/369, 257/371, 257/379, 257/380, 365/72, 365/156, 365/181, 365/190, 365/53
• US Class Current: 326/9
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits

Abstract

CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a way that they block and dissipate the erroneous signal. The added transistor structures are made immune to SEU by placing them in well diffusions that are separate from the rest of the circuit and biasing those wells such that the electric fields surrounding the transistors are very low in comparison to the rest of the circuit. Signal blocking is achieved with an SEU immune transistor that is in an “off” state whenever other circuit transistors that deliver signals through it are potentially sensitive to SEU. Dissipation is achieved with either a resistor or low current drive transistor that spreads the SEU signal out over time thereby reducing its voltage change to an acceptable level.

Claims

1. An SEU signal blocking and dissipation subcircuit comprised of:

(a) a blocking subciruit using transistors that are entirely of type PMOS which are all contained within a single n-well, said blocking subcircuit having one external source node which is connected to the n-well and sources of one or more of the subcircuit'"'"'s transistors, one external drain node which is connected to one or more drains of the subcircuit'"'"'s transistors, and a set of external gate nodes connected to the subcircuit'"'"'s transistor gates and having bias applied to the external gate nodes such that whenever any circuit connected to the blocking subcircuit'"'"'s external source node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external source node to the external drain node will be in a high impedance (off) state; and

(b) a shunt subcircuit connected between the blocking subcircuit'"'"'s external source node and another circuit node which has a static bias potential with respect to the blocking subcircuit'"'"'s external drain node the magnitude of which is less than 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit'"'"'s external drain node to the negative circuit power supply or ground.

2. An SEU signal blocking and dissipation subcircuit comprised of:

(a) a blocking subcircuit using transistors that are entirely of type NMOS which are all contained within a single p-well, said blocking subcircuit having one external source node which is connected to the p-well and sources of one or more of the subcircuit'"'"'s transistors, one external drain node which is connected to one or more drains of the subcircuit'"'"'s transistors, and a set of external gate nodes connected to the subcircuit'"'"'s transistor gates and having bias applied to the external gate nodes such that whenever any circuit connected to the blocking subcircuit'"'"'s external source node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external source node to the external drain node will be in a high impedance (off) state; and

(b) a shunt subcircuit connected between the blocking subcircuit'"'"'s external source node and another circuit node which has a static bias potential with respect to the blocking subcircuit'"'"'s external drain node the magnitude of which is less than 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit'"'"'s external drain node to the positive circuit power supply or Vdd.

3. An SEU signal blocking and dissipation subcircuit comprised of:

(a) a blocking subcircuit using transistors that are entirely of type NMOS which are all contained within a single p-well, said blocking subcircuit having one external source node which is connected to the sources of one or more of the subcircuit'"'"'s transistors, one external drain node which is connected to one or more drains of the subcircuit'"'"'s transistors, an external p-well node connected to the common p-well, and a set of external gate nodes connected to the subcircuit'"'"'s transistor gates and having bias applied to the p-well node such that the blocking subcircuit'"'"'s p-well is at a potential with respect to the blocking subcircuit'"'"'s external source node the magnitude of which is less than 40% of the potential from the supply voltage to ground and having bias applied to said blocking subcircuit'"'"'s external gate nodes such that whenever any circuit connected to the blocking subcircuit'"'"'s external drain node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external drain node to the external source node will be in a high impedance (off) state; and

(b) a shunt subcircuit connected between the blocking subcircuit'"'"'s external drain node and another circuit node which has a static bias potential with respect to the blocking subcircuit'"'"'s external source node the magnitude of which is less than 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit'"'"'s external source node to the negative circuit power supply or ground.

4. An SEU signal blocking and dissipation subcircuit comprised of:

(a) a blocking subcircuit using transistors that are entirely of type PMOS which are all contained within a single n-well, said blocking subcircuit having one external source node which is connected to the sources of one or more of the subcircuit'"'"'s transistors, one external drain node which is connected to one or more drains of the subcircuit'"'"'s transistors, an external n-well node connected to the common n-well, and a set of external gate nodes connected to the subcircuit'"'"'s transistor gates and having bias applied to the blocking subcircuit'"'"'s n-well node such that the n-well is at a potential with respect to the blocking subcircuit'"'"'s external source node the magnitude of which is less than 40% of the potential from the supply voltage to ground and having bias applied to said blocking subcircuit'"'"'s external gate nodes such that whenever any circuit connected to the blocking subcircuit'"'"'s external drain node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external drain node to the external source node will be in a high impedance (off) state; and

(b) a shunt subcircuit connected between the blocking subcircuit'"'"'s external drain node and another circuit node which has a static bias potential with respect to the blocking subcircuit'"'"'s external source node the magnitude of which is less then 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit'"'"'s external source node to the positive circuit power supply or Vdd.

5. A circuit comprising in combination:

(a) a plurality of single event upset (SEU) sensitive transistors;

(b) a circuit node driven by said plurality of single event upset (SEU) sensitive transistors;

(c) at least one single event (SEU) immune transistor disposed between said single event upset (SEU) sensitive transistors and said circuit node driven by said plurality of single event (SEU) sensitive transistors;

(d) and with bias being supplied to the single event upset (SEU) immune transistor(s) such that it is in a high impedance state at any time that bias to said plurality of single event upset (SEU) sensitive transistors places any of said plurality of single event upset (SEU) sensitive transistors in a single event upset (SEU) sensitive state.

6. A single event upset (SEU) hardened circuit comprising in combination:

(a) a plurality of transistors connected to a plurality of output logic nodes; and

(b) said plurality of transistors connected to said plurality of output nodes comprise transistors within isolated wells having no gate, drain, source, or well node of said plurality of transistor connected in common with VDD or VSS.

7. An isolated well transistor circuit which has neither drain, source, gate, nor well nodes connected in common with either VDD or VSS for mitigation of single event upsets comprising dynamic logic which hardens the logic to corruption from transients causes by charged particle radiation.