Buffer with stable trip point

• US 6,278,295 B1
• Filed: 02/10/1998
• Issued: 08/21/2001
• Est. Priority Date: 02/10/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lovett, Simon J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/021,461
• Time in Patent Office: 1,288 Days
• Field of Search: 326/39, 326/40, 326/41, 326/83, 326/112, 326/119, 326/121, 326/57, 326/58, 326/31, 326/32, 326/33, 326/34
• US Class Current: 326/83
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage. Alternatively, the compensating arrangement may include a first and a second pair of devices of a first and second conductivity type connected in parallel and disposed in the pull-up and pull-down paths. The devices of the first conductivity type are connected at their control electrodes to the supply voltage and the devices of the second conductivity type are connected, at their control electrodes, to ground. The DC trip point is then stabilized at about nominal over at least process skew and variations in supply voltage.

Claims

1. A buffer circuit, comprising:

an input stage, comprising an input node, a first pull-up transistor, a first pull-down transistor, and an output node;

a control circuit configured to (i) couple said first pull-up transistor to a first supply voltage and (ii) couple said output node to a second supply voltage; and

a stabilizing circuit comprising first and second stabilizing elements, each in series with at least one of said first pull-up transistor and said first pull-down transistor, wherein said first stabilizing element comprises a first p-channel transistor coupled in parallel with a first n-channel transistor slower than said first p-channel transistor.

2. The buffer circuit of claim 1, wherein said stabilizing circuit comprises (i) said first p-channel transistor in a pull-up path and (ii) a second n-channel transistor in a pull-down path, each being independently coupled to at least one source/drain terminal of at least one of said first pull-up transistor and said first pull-down transistor.

3. The buffer circuit of claim 2, further comprising an output stage configured to generate an output signal in response to a voltage at said output node.

4. The buffer circuit of claim 2, wherein said stabilizing circuit is configured to (i) increase a pull down current through said source/drain terminal of said first pull-down transistor in response to said first supply voltage, (ii) decrease a pull down current through said source/drain terminals of said pull-down transistor in response to said first supply voltage, or (iii) both (i) and (ii).

5. The buffer circuit of claim 2, wherein said stabilizing circuit is configured to (i) increase a pull-up current through a first output of said control circuit and through said source/drain of said first pull-up transistor in response to said second supply voltage, (ii) decrease the pull-up current through said first output of said control circuit and through said source/drain of said first pull-up transistor in response to said second supply voltage, or (iii) both (i) and (ii).

6. The buffer circuit of claim 4, wherein said stabilizing circuit is configured to (i) increase a pull-up current through a first output of said control circuit and through said source/drain terminal of said first pull-up transistor in response to said second supply voltage, (ii) decrease the pull-up current through said first output of said control circuit and through said source/drain of said first pull-up transistor in response to said second supply voltage, or (iii) both (i) and (ii).

7. The buffer circuit of claim 2, wherein said first p-channel transistor and said first n-channel transistor slower than said first p-channel transistor are coupled in parallel between said output node and one source/drain terminal of said first pull-up transistor.

8. The buffer circuit of claim 7, wherein said p-channel transistor faster than said n-channel transistor and said n-channel transistor are coupled in parallel between said output node and one source/drain terminal of said first pull-down transistor.

9. The buffer circuit of claim 7, wherein the gate of said slower n-channel transistor is coupled to said first supply voltage.

10. A buffer circuit, comprising:

an input stage, comprising an input node, a first pull-up transistor, a first pull-down transistor, and an output node;

a control circuit configured to (i) couple said first pull-up transistor to a first supply voltage and (ii) couple said output node to a second supply voltage; and

a stabilizing circuit comprising first and second stabilizing elements, each in series with at least one of said first pull-up transistor and said first pull-down transistor, wherein said second stabilizing element comprises an n-channel transistor coupled in parallel with a p-channel transistor faster than said n-channel transistor.

11. The buffer circuit of claim 10, wherein the gate of said faster p-channel transistor is coupled to said second supply voltage.