Inverter circuit with multilayer piezoelectric transformer

• US 6,278,625 B1
• Filed: 07/13/2000
• Issued: 08/21/2001
• Est. Priority Date: 07/13/2000
• Status: Expired due to Fees

• Current Assignee: Face International Corp.
• Original Assignee: Face International Corp.
• Inventors: Boyd, Clark Davis
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Laxton, Gary L.
• Application Number:
  US09/615,234
• Time in Patent Office: 404 Days
• Field of Search: 363/132, 363/98, 363/97, 363/95, 310/318, 310/319, 310/314, 315/209.PZ, 323/299, 323/301
• US Class Current: 363/132
• CPC Class Codes: H02M 7/48 using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: H05B 41/2827 using specially adapted components in the load circuit, e.g. feed-back transformers, piezoelectric transformers; using specially adapted load circuit configurations
• CPC Class Codes: H10N 30/40 with electrical input and electrical output, e.g. functioning as transformers
• CPC Class Codes: H10N 30/804 for piezoelectric transformers

Abstract

An inverter circuit is provided using a voltage converter having multiple layers of piezoelectric ceramic. More specifically, the present invention provides an inverter circuit for a Cold Cathode Fluorescent Lamp (CCFL) incorporating a multilayer piezoelectric transformer that uses the longitudinal resonant vibration mode for step-up voltage conversion. The transformer is driven by a FET half-bridge connected to an oscillator through dual current buffers, one current buffer being driven through and a level shifter and charge pump.

Claims

1. A circuit for producing an alternating current, comprising:

a power source;

an oscillator array having an input side and an output side;

said power source being connected to said input side of said oscillator array;

a first current buffer having an input side and an output side;

said input side of said first current buffer being connected to said output side of said oscillator array;

a level shifter having an input side and an output side;

said input side of said level shifter being connected to said output side of said oscillator array in parallel with said first current buffer;

a second current buffer having an input side and an output side;

said input side of said second current buffer being connected in series with said output side of said level shifter;

a FET half-bridge comprising a first FET and a second FET;

a drain of said first FET being connected by an output conductor of said FET half-bridge to a source of said second FET;

a gate of said first FET being connected to said output side of said first current buffer;

a gate of said second FET being connected to said output side of said second current buffer;

an inductor having an input side and an output side;

said input side of said inductor being connected to said output conductor of said FET half-bridge; and

a piezoelectric transformer having a first input terminal, a grounded second input terminal and an output terminal;

said first input terminal being connected to said output side of said inductor.

2. The circuit according to claim 1, further comprising;

a charge pump having an input side and an output side;

said input side of said charge pump being connected to said output conductor of said FET half-bridge;

said input side of said charge pump being connected to a drain of said second FET in said half-bridge;

said output side of said charge pump being connected to said level shifter; and

said output side of said charge pump being connected to said second current buffer.

3. The circuit according to claim 2,

wherein said oscillator array comprises an inverter array;

and wherein an output signal of said oscillator array comprises an electrical signal oscillating between a ground value and a positive value.

4. The circuit according to claim 3,

wherein said oscillator array further comprises a first resistor in series with a first capacitor;

said first resistor and said first capacitor being connected in parallel with a first inverter of said inverter array.

5. The circuit according to claim 4,

wherein said oscillator array further comprises:

a second inverter of said inverter array connected in series with said first inverter; and

a second resistor connected in series with said first capacitor;

said second resistor and said first capacitor being connected in parallel with said second inverter.

6. The circuit according to claim 5,

wherein said level shifter further comprises:

a first BJT;

said first BJT being a PNP type BJT having a collector connected to said input side of said second current buffer;

said first BJT having an emitter connected to ground;

a third resistor connected in series between said output side of said oscillator array and a base of said first BJT; and

a fourth resistor connected in series between said output side of said charge pump and said collector of said first BJT.

7. The circuit according to claim 6,

wherein said first current buffer further comprises:

a second capacitor having first and second sides;

a second positive voltage source;

a second BJT;

said second BJT being a NPN type BJT having a base connected to said output side of said oscillator array;

said second BJT having a collector connected to said first side of said second capacitor;

said second BJT having said collector connected to said second positive voltage source; and

a third BJT;

said third BJT being a PNP type BJT having a base connected to said output side of said oscillator array;

said third BJT having a collector connected to said second side of said second capacitor;

said third BJT having said collector connected to ground;

said output side of said first current buffer being at a junction of an emitter of said third BJT with an emitter of said second BJT.

8. The circuit according to claim 7,

wherein said second current buffer further comprises:

a third capacitor having first and second sides;

a fourth BJT;

said fourth BJT being a NPN type BJT having a base connected to said collector of said first BJT;

said fourth BJT having a collector connected to said first side of said third capacitor;

said fourth BJT having said collector connected to said output side of said charge pump; and

a fifth BJT;

said fifth BJT being a PNP type BJT having a base connected to said collector of said first BJT;

said fifth BJT having a collector connected to said second side of said third capacitor;

said fifth BJT having said collector connected to ground;

said output side of said second current buffer being at a junction of an emitter of said fifth BJT and an emitter of said fourth BJT.

9. The circuit according to claim 8,

wherein said charge pump further comprises:

a first diode having a cathode connected to a drain of said second FET in said half-bridge;

a third positive voltage source connected to said drain of said second FET in said half-bridge;

a fourth grounded capacitor having an ungrounded side connected to said fourth resistor and to said collector of said fourth BJT;

a second diode having an anode connected to said ungrounded side of said fourth capacitor and having a cathode connected to an anode of said first diode; and

a fifth capacitor having a first side and a second side;

said first side of said fifth capacitor being connected to said output side of said half-bridge and to said input side of said inductor;

said second side of said fifth capacitor being connected to said cathode of said second diode.

10. The circuit according to claim 9, further comprising:

a gas discharge lamp having a high voltage side and a low voltage side;

said high voltage side of said gas discharge lamp being connected to said output side of said piezoelectric transformer; and

said low voltage side of said gas discharge lamp being connected to ground.

11. The circuit according to claim 10, further comprising:

a feed back subcircuit connected between said low voltage side of said gas discharge lamp and said input side of said oscillator array.

12. The circuit according to claim 11, wherein said feedback subcircuit comprises:

a third diode having a grounded cathode and having an anode connected to said low voltage side of said gas discharge lamp;

a sixth BJT having a base connected to said anode of said third diode and to said low voltage side of said gas discharge lamp;

a positive voltage source connected to a collector of said sixth BJT; and

a fifth resistor having first and second sides;

said first side of said fifth resistor being connected to said collector of said sixth BJT;

said second side of said fifth resistor being connected to said input side of said oscillator array.

13. The circuit according to claim 12,

wherein said oscillator array further comprises a third inverter of said inverter array connected in parallel with said first inverter.

14. The circuit according to claim 13,

wherein said oscillator array further comprises a fourth inverter of said inverter array connected in series between said second inverter and said first and third parallel inverters.

15. The circuit according to claim 14,

wherein said second side of said fifth resistor is connected to said input side of said oscillator array between said second resistor and said second inverter.

16. The circuit according to claim 14,

wherein said second side of said fifth resistor is connected to said input side of said oscillator array between said first resistor and said first capacitor.

17. The circuit according to claim 1, wherein said piezoelectric transformer comprises:

a first input electroactive layer having first and second opposing electroded major faces an d first and second opposing minor faces and polarized such that upon application of voltage across said first and second opposing electroded major faces,

said first input electroactive layer deforms in a longitudinal direction parallel to said first and second opposing electroded major faces and perpendicular to said first and second opposing minor faces;

an output electroactive layer having first and second opposing major faces, first and second opposing electroded minor faces, third and fourth opposing minor faces, and a central output electrode bonded to said output electroactive layer between said first and second opposing electroded minor faces;

said output electroactive layer having a first output portion between said central output electrode and said first electroded minor face, said first output portion being polarized in a direction normal to said first electroded minor face;

said output electroactive layer having a second output portion between said central output electrode and said second electroded minor face, said second output portion being polarized in a direction normal to said second electroded minor face; and

a dielectric layer having first and second opposing major faces;

said first major face of said dielectric layer being bonded to said first electroded major face of said input electroactive layer;

said second major face of said dielectric layer being bonded to said first major face of said output electroactive layer.

18. The circuit according to claim 17, wherein said piezoelectric transformer further comprises:

a second input electroactive layer having first and second opposing electroded major faces and polarized such that upon application of a voltage is across said first and second opposing electroded major faces, said second input electroactive layer deforms in said longitudinal direction parallel to said first and second opposing major faces;

said first electroded major face of said second input electroactive layer being bonded to said second electroded major face of said first input electroactive layer.