System and method for reducing deinterleaver memory requirements through chunk allocation

• US 6,278,715 B1
• Filed: 11/05/1998
• Issued: 08/21/2001
• Est. Priority Date: 11/05/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Hansquine, David
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): Sam, Phirin
• Application Number:
  US09/187,686
• Time in Patent Office: 1,020 Days
• Field of Search: 370/428, 370/412, 370/413, 370/415, 370/417, 370/394, 370/393, 370/329, 370/419, 370/420, 370/429, 375/246, 375/353, 375/262, 375/265, 375/341, 375/372, 714/755, 714/756, 714/759, 714/760, 714/766, 714/784, 714/791, 714/793, 714/795
• US Class Current: 370/428
• CPC Class Codes: H03M 13/2782 Interleaver implementations, which reduce the amount of required interleaving memory
• CPC Class Codes: H03M 13/2785 Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location

Abstract

A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.

Claims

1. A method of reducing memory requirements in a system including at least one deinterleaver and a decoder, said system being constructed and arranged to receive a plurality of symbols for a plurality of channels, said method comprising:

making a plurality of buffers in a memory available for receiving said symbols, each of said buffers including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;

receiving and storing at least a portion of the symbols from the frame period for at least some of said plurality of channels into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;

decoding said symbols received during frame periods for said at least some of said plurality of channels after said symbols are stored into said chunks during complete ones of said frame periods; and

making said chunks, which store said decoded symbols, available for receiving additional symbols.

2. A method according to claim 1, wherein a total amount of capacity of said buffers for storing said received symbols for said channels is less than a total amount of capacity of said buffers required to store two complete ones of said frame periods of said symbols for all of said channels.

3. A method according to claim 1, wherein decoding said symbols received during said frame periods is performed serially.

4. A method according to claim 1, wherein a number of said plurality of said channels is eight channels.

5. A method according to claim 1, wherein a number of chunks, having a total cumulative capacity of 384 symbols, is made available for storing said additional symbols for each of said channels decoded during each of said frame periods.

6. A method according to claim 1, wherein each of said chunks has a capacity to store 192 symbols.

7. A combination, including at least one deinterleaver and a decoder, constructed and arranged to receive a plurality of symbols for a plurality of channels, said combination comprising:

at least one memory including a plurality of buffer areas available for receiving said symbols, each of said buffer areas including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;

means for receiving and storing said symbols, received during at least a portion of frame periods, for at least some of said plurality of channels into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;

means for decoding said symbols for said at least some of said plurality of channels after said symbols for said at least some of said plurality of channels are received into said chunks during complete ones of said frame periods; and

means for making said chunks, which store said decoded symbols, available for receiving additional symbols.

8. A combination according to claim 7, wherein a total amount of capacity of said buffer areas for storing said received plurality of symbols for said plurality of channels is less than a total amount of capacity of said buffer areas required to store said symbols for two complete frame periods for all of said channels.

9. A combination according to claim 7, wherein said decoding means is arranged to decode said symbols serially.

10. A combination according to claim 7, wherein a number of said channels is eight channels.

11. A combination according to claim 7, wherein a number of chunks, having a total cumulative capacity of 384 symbols, is made available for storing said additional symbols for each of said channels decoded during each of said frame periods.

12. A combination according to claim 7, wherein each of said chunks has a capacity to store 192 symbols.

21. A combination according to claim 7, further comprising:

means for identifying a buffer from which to read, from said plurality of buffers, based on a frame number and an indication of a channel number.

22. A combination according to claim 7, further comprising:

means for identifying a buffer in which to write, from said plurality of buffers, based on a frame number and an indication of a channel number.

13. A combination constructed and arranged to receive a plurality of symbols for a plurality of channels, comprising:

at least one memory including a plurality of buffer areas available for receiving said symbols, each of said buffer areas including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;

at least one deinterleaver being arranged to receive said symbols, for at least some of said plurality of channels, during at least a portion of frame periods, said at least one deinterleaver being arranged to store said received symbols into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;

a decoder being arranged to decode said symbols for said at least some of said plurality of channels after said symbols for said at least some of said plurality of channels are received into said chunks from said at least one deinterleaver during complete ones of said frame periods; and

means for making said chunks, which store said decoded symbols, available for receiving additional symbols.

14. A combination according to claim 13, wherein a total amount of capacity of said buffer areas for storing said received plurality of symbols for said plurality of channels is less than a total amount of capacity of said buffer areas required to store said symbols for two complete frame periods for all of said channels.

15. A combination according to claim 13, wherein said decoder is arranged to decode said symbols serially.

16. A combination according to claim 13, wherein a number of said channels is eight channels.

17. A combination according to claim 13, wherein a number of chunks, having a total cumulative capacity of 384 symbols, is made available for storing said additional symbols for each of said channels decoded during each of said frame periods.

18. A combination according to claim 13, wherein each of said chunks has a capacity to store 192 symbols.

19. A combination according to claim 13, further including control circuitry, said control circuitry comprising:

a counter comprising at least four bits, said counter being arranged to be incremented every first predetermined time interval;

a register arranged to receive at least three bits of said at least four bits of said counter, said at least three bits of said counter indicating a particular frame period, said register being enabled to receive said at least three bits every second predetermined time period, said second predetermined time period being larger than said first predetermined time period;

a first concatenater arranged to receive said at least three bits from said register, a RDChannel indicator, arranged to provide an indication of at least a portion of a channel number to be read by said decoder, and a RD-Second half indicator from said decoder, said RD-Second half indicator being arranged to provide an indication of whether a first or a second half of a frame of symbols is to be read;

a second concatenater arranged to receive said at least four bits from said counter during each of said first predetermined time periods and a WR-Channel indicator, arranged to provide an indication of a channel number corresponding to at least one channel being received; and

a multiplexer arranged to receive an output from said first concatenater and an output from said second concatenater, said multiplexer being arranged to select as an output one of said received output from said first concatenater and said received output from said second concatenater, based on a signal provided to said multiplexer.

20. A combination according to claim 13, further including control circuitry, said control circuitry comprising:

a counter comprising at least four bits, said counter being arranged to be incremented every first predetermined time interval;

a subtract-by-1 block arranged to receive at least three bits of said at least four bits of said counter, said at least three bits of said counter indicating a particular frame period;

a first concatenater arranged to receive an output from said subtract-by-1 block, a RDChannel indicator, arranged to provide an indication of at least a portion of a channel number to be read by said decoder, and a RD-Second half indicator from said decoder, said RD-Second half indicator being arranged to provide an indication of whether a first or a second half of a frame of symbols is to be read;

a second concatenater arranged to receive said at least four bits from said counter during each of said first predetermined time periods and a WR-Channel indicator, arranged to provide an indication of a channel number corresponding to at least one channel being received; and

a multiplexer arranged to receive an output from said first concatenater and an output from said second concatenater, said multiplexer being arranged to select as an output one of said received output from said first concatenater and said received output from said second concatenater, based on a signal provided to said multiplexer.

23. A combination according to claim 13, further comprising:

means for identifying a buffer from which to read, from said plurality of buffers, based on a frame number and an indication of a channel number.

24. A combination according to claim 13, further comprising:

means for identifying a buffer to which to write, from said plurality of buffers, based on a frame number and an indication of a channel number.