System and method for reducing deinterleaver memory requirements through chunk allocation
First Claim
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1. A method of reducing memory requirements in a system including at least one deinterleaver and a decoder, said system being constructed and arranged to receive a plurality of symbols for a plurality of channels, said method comprising:
- making a plurality of buffers in a memory available for receiving said symbols, each of said buffers including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;
receiving and storing at least a portion of the symbols from the frame period for at least some of said plurality of channels into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;
decoding said symbols received during frame periods for said at least some of said plurality of channels after said symbols are stored into said chunks during complete ones of said frame periods; and
making said chunks, which store said decoded symbols, available for receiving additional symbols.
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Abstract
A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.
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Citations
24 Claims
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1. A method of reducing memory requirements in a system including at least one deinterleaver and a decoder, said system being constructed and arranged to receive a plurality of symbols for a plurality of channels, said method comprising:
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making a plurality of buffers in a memory available for receiving said symbols, each of said buffers including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;
receiving and storing at least a portion of the symbols from the frame period for at least some of said plurality of channels into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;
decoding said symbols received during frame periods for said at least some of said plurality of channels after said symbols are stored into said chunks during complete ones of said frame periods; and
making said chunks, which store said decoded symbols, available for receiving additional symbols. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A combination, including at least one deinterleaver and a decoder, constructed and arranged to receive a plurality of symbols for a plurality of channels, said combination comprising:
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at least one memory including a plurality of buffer areas available for receiving said symbols, each of said buffer areas including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;
means for receiving and storing said symbols, received during at least a portion of frame periods, for at least some of said plurality of channels into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;
means for decoding said symbols for said at least some of said plurality of channels after said symbols for said at least some of said plurality of channels are received into said chunks during complete ones of said frame periods; and
means for making said chunks, which store said decoded symbols, available for receiving additional symbols. - View Dependent Claims (8, 9, 10, 11, 12, 21, 22)
means for identifying a buffer from which to read, from said plurality of buffers, based on a frame number and an indication of a channel number.
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22. A combination according to claim 7, further comprising:
means for identifying a buffer in which to write, from said plurality of buffers, based on a frame number and an indication of a channel number.
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13. A combination constructed and arranged to receive a plurality of symbols for a plurality of channels, comprising:
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at least one memory including a plurality of buffer areas available for receiving said symbols, each of said buffer areas including a plurality of chunks, each chunk having a minimum of n/x locations, where n represents a number of symbols in a frame period and x represents a number of channels;
at least one deinterleaver being arranged to receive said symbols, for at least some of said plurality of channels, during at least a portion of frame periods, said at least one deinterleaver being arranged to store said received symbols into corresponding ones of said chunks, each of said corresponding ones of said chunks storing symbols of only a corresponding one of said channels;
a decoder being arranged to decode said symbols for said at least some of said plurality of channels after said symbols for said at least some of said plurality of channels are received into said chunks from said at least one deinterleaver during complete ones of said frame periods; and
means for making said chunks, which store said decoded symbols, available for receiving additional symbols. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 23, 24)
a counter comprising at least four bits, said counter being arranged to be incremented every first predetermined time interval;
a register arranged to receive at least three bits of said at least four bits of said counter, said at least three bits of said counter indicating a particular frame period, said register being enabled to receive said at least three bits every second predetermined time period, said second predetermined time period being larger than said first predetermined time period;
a first concatenater arranged to receive said at least three bits from said register, a RDChannel indicator, arranged to provide an indication of at least a portion of a channel number to be read by said decoder, and a RD-Second half indicator from said decoder, said RD-Second half indicator being arranged to provide an indication of whether a first or a second half of a frame of symbols is to be read;
a second concatenater arranged to receive said at least four bits from said counter during each of said first predetermined time periods and a WR-Channel indicator, arranged to provide an indication of a channel number corresponding to at least one channel being received; and
a multiplexer arranged to receive an output from said first concatenater and an output from said second concatenater, said multiplexer being arranged to select as an output one of said received output from said first concatenater and said received output from said second concatenater, based on a signal provided to said multiplexer.
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20. A combination according to claim 13, further including control circuitry, said control circuitry comprising:
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a counter comprising at least four bits, said counter being arranged to be incremented every first predetermined time interval;
a subtract-by-1 block arranged to receive at least three bits of said at least four bits of said counter, said at least three bits of said counter indicating a particular frame period;
a first concatenater arranged to receive an output from said subtract-by-1 block, a RDChannel indicator, arranged to provide an indication of at least a portion of a channel number to be read by said decoder, and a RD-Second half indicator from said decoder, said RD-Second half indicator being arranged to provide an indication of whether a first or a second half of a frame of symbols is to be read;
a second concatenater arranged to receive said at least four bits from said counter during each of said first predetermined time periods and a WR-Channel indicator, arranged to provide an indication of a channel number corresponding to at least one channel being received; and
a multiplexer arranged to receive an output from said first concatenater and an output from said second concatenater, said multiplexer being arranged to select as an output one of said received output from said first concatenater and said received output from said second concatenater, based on a signal provided to said multiplexer.
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23. A combination according to claim 13, further comprising:
means for identifying a buffer from which to read, from said plurality of buffers, based on a frame number and an indication of a channel number.
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24. A combination according to claim 13, further comprising:
means for identifying a buffer to which to write, from said plurality of buffers, based on a frame number and an indication of a channel number.
Specification