System wake-up based on joystick movement

• US 6,279,048 B1
• Filed: 07/07/1998
• Issued: 08/21/2001
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Velingker, Avinash, Soto, Walter G., Potts, David Lawson, Fadavi-Ardekani, Jalil
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/110,673
• Time in Patent Office: 1,141 Days
• Field of Search: 710/2, 710/5, 710/14, 710/15, 710/62, 710/18, 713/300, 713/310, 713/323, 713/324, 273/148.R, 345/161
• US Class Current: 710/15
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3259 Power saving in cursor control device, e.g. mouse, joystick, trackball
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0278 Band edge detection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The present invention provides a game port interface having a second processor interface in addition to an otherwise conventional first processor interface such that a second processor may directly poll the game port interface to detect movement of a joystick device while a first, host processor is in a low power mode. Thus, the second processor may identify movement in the joystick and initiate a wake up sequence in the first, host processor via a communication path between the two processor interfaces. The additional processor interface allows the second processor to poll the joystick without interfering with the normal operation of the joystick. The present invention provides the power savings benefits of maintaining a host processor in a low power mode while at the same allowing another processor which may or may not be in a reduced power mode to detect movement of the joystick and initiate a wake up sequence in the host processor in response thereto.

Claims

1. A system, comprising:

a host processor;

a second processor; and

a joystick interface with a game port;

wherein said second processor is adapted to sense a change in a position of a joystick coupled to said joystick interface while said host processor is in a sleep mode, and to initiate a wake-up procedure in said host processor upon sensing said change in said position of said joystick.

2. A game port interface comprising:

a timing circuit to sense a change in a condition of a joystick interfacing with said game port interface;

a first data bus interface to provide a first processor access to said condition of said joystick; and

a second data bus interface to provide a second processor access to said condition of said joystick;

wherein said second processor is adapted to be woken-up from a sleep mode upon a change in condition of said joystick.

3. The game port interface according to claim 2, wherein:

said first data bus interface includes a communication path with said second data bus interface to allow communication from said second processor to said first processor.

4. The game port interface according to claim 2, wherein:

said second processor is a digital signal processor.

5. The game port interface according to claim 2, further comprising:

a logic circuit to allow one of a first polling signal from said first processor and a second polling signal from said second processor to trigger said game port interface.

6. A method of polling a game port interface with a joystick, comprising:

adapting a second processor to sense a change in a position of said joystick coupled to a joystick interface of said game port while a host processor is in a sleep mode, and to initiate a wake-up procedure in said host processor upon sensing said change in said position of said joystick;

placing said host processor in a low power mode; and

polling said joystick interface of said game port from said second processor.

7. The method of polling a game port interface with a joystick according to claim 6, further comprising:

polling said joystick interface of said game port from said host processor.

8. The method of polling a game port interface with a joystick according to claim 7, wherein:

said low power mode halts polling from said host processor to said joystick interface.

9. The method of polling a game port interface with a joystick according to claim 7, further comprising:

placing said second processor in a low power mode.

10. Apparatus for polling a game port interface with a joystick, comprising:

means for adapting a second processor to sense a change in position of said joystick coupled to a joystick interface of said game port while a host processor is in a sleep mode, and for initiating a wake-up procedure in said host processor upon sensing said change in said position of said joystick;

means for placing said host processor in a low power mode; and

means for polling said joystick interface of said game port from said second processor.

11. The apparatus for polling a game port interface with a joystick according to claim 10, further comprising:

means for polling said joystick interface of said game port from said host processor.

12. The apparatus for polling a game port interface with a joystick according to claim 11, wherein:

said low power mode halts polling from said host processor to said joystick interface.

13. The apparatus for polling a game port interface with a joystick according to claim 11, further comprising:

means for placing said second processor in a low power mode.