Dynamic sizing of FIFOs and packets in high speed serial bus applications

• US 6,279,052 B1
• Filed: 01/13/1998
• Issued: 08/21/2001
• Est. Priority Date: 01/13/1998
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Upadrastra, Prasad V.
• Primary Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US09/006,511
• Time in Patent Office: 1,316 Days
• Field of Search: 709/232-235, 710/22-30, 710/55-57
• US Class Current: 710/22
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An apparatus for conducting serial bus transactions. The embodiments of the invention permit a reduction in the die space allocated to buffering in chipsets supporting a high speed serial bus. Buffering currently occupies a substantial proportion of total die area. That proportion is expected to increase as the serial protocols implemented gain speed. Accordingly, control of buffers sizes is expected to provide a significant cost benefit both now and in the future. In one embodiment, a transceiver is provided. A plurality of FIFOs are allocatable from a shared buffer pool, each FIFO corresponding to a serial bus transaction type. A plurality of direct memory access controllers (DMAs) are coupled to the FIFO and fill or empty the FIFO. A link layer provides an interface between the transceiver and the FIFOs permitting the transceiver to conduct transactions to and from the FIFOs. In another embodiment of the invention, again a transceiver is provided. A FIFO smaller than a default packet size of an associated transaction type is employed. A link layer provides an interface between the small FIFO and the transceiver. The link layer also sets a control register to dictate packet size so that an upstream system can handle transfers of the packet size eventhough constrained by the small FIFO.

Claims

1. An apparatus comprising:

a transceiver;

a buffer pool dynamically allocatable between FIFOs for a plurality of transaction types;

a plurality of DMA controllers to fill and empty the FIFOs and coupled to the FIFOs allocated from the buffer pool; and

a link layer interfacing between the FIFOs and the transceiver such that the transceiver can conduct serial bus transactions to and from the FIFOs.

2. The apparatus of claim 1 further comprising:

a plurality of control registers coupled to the buffer pool setable to define a size of the FIFOs for each transaction type.

3. A system comprising:

a serial bus;

a processor;

a serial bus driver executing on the processor, the driver packetizing data to be transferred over the serial bus wherein a packet size is dynamically setable within an acceptable service range;

a memory controller coupled to the processor and a memory;

a plurality of direct memory access controllers (DMA'"'"'s) coupled to the memory controller and a plurality of FIFOs, each FIFO of the plurality corresponding to a serial bus transaction type and having a size smaller than a default packet size of a corresponding transaction type;

a transceiver to transmit and receive packets across a serial bus; and

a link layer interfacing between the FIFOs and the transceiver.

4. The system of claim 3 wherein the FIFOs are dynamically allocatable from a shared buffer pool.

5. The system of claim 3 wherein the link layer reduces the packet size when resource scarcity in an upstream subsystem prevents real time handling of packets of an optimum size.

6. The system of claim 5 wherein the link layer interrupts the driver when the speed of the upstream subsystem fails to exceed the speed of transfers on the serial bus.

7. An apparatus comprising:

a transceiver;

a FIFO smaller than a default packet size of an associated transaction type;

a link layer interfacing between the FIFOs and the transceiver such that the transceiver can conduct serial bus transactions to and from the FIFOs; and

a control register setable by the link layer to dictate a packet size wherein the packet size is reduced if an upstream system cannot handle transfers at the existing packet size.

8. The apparatus of claim 7 wherein transfer of a packet begins before the packet is received entirely by the FIFO.

9. The apparatus of claim 7 wherein the link layer signals a downstream subsystem to discard a packet if the link layer exhausts data in the FIFO without reaching an end of the packet.

10. The apparatus of claim 7 wherein the link layer interrupts the driver when the speed of the upstream subsystem fails to exceed the speed of transfers on the serial bus.