Universal serial bus peripheral bridge simulates a device disconnect condition to a host when the device is in a not-ready condition to avoid wasting bus resources

• US 6,279,060 B1
• Filed: 12/04/1998
• Issued: 08/21/2001
• Est. Priority Date: 12/04/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: In-System Design Incorporated (Infineon Technologies AG)
• Inventors: Luke, David D., Luttmann, Eric J., Richter, Ronald J., Gilbert, David C.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/205,558
• Time in Patent Office: 991 Days
• Field of Search: 710/8, 710/10, 710/11, 710/14, 710/15, 710/62, 710/63, 710/64, 710/129
• US Class Current: 710/64
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/4002 Universal serial bus hub with a single upstream port

Abstract

A Universal Serial Bus (USB) peripheral bridge and method for operation are disclosed. The bridge simulates a device disconnect condition to its upstream USB hub or host, even though it remains connected and powered, when its associated peripheral is not ready to communicate, powered off, or physically disconnected. For an IEEE-1284-1994 peripheral connection, the bridge senses the condition of the PLH peripheral line. If the PLH line is deasserted or floating, the bridge simulates a device disconnect condition by either allowing its upstream hub or host to take the D+ data line low, or taking the line low itself. By not allowing itself to be enumerated on the USB unless its associated peripheral is ready, the bridge avoids confusion at the host and wasted bus resources. At the same time, the bridge may remain physically connected to the host regardless of the state of the peripheral, even if the bridge is powered from the host.

Claims

1. A Universal Serial Bus to parallel bus bridge comprising:

a D+ and a D−

serial bus connection;

a parallel bus connection; and

a serial bus disconnect circuit that senses the existence of a not-ready condition at said parallel bus connection, and responds to said not-ready condition by providing for a single-ended zero state on said D+ and D−

serial bus connections.

2. A Universal Serial Bus to parallel bus bridge comprising:

a D+ and a D−

serial bus connection;

a peripheral-device-ready signal parallel bus connection; and

a serial bus disconnect circuit connected to said peripheral-device-ready signal parallel bus connection, said serial bus disconnect circuit responding to a floating condition or a not-ready signal appearing at said peripheral-device-ready signal parallel bus connection by providing for a single-ended zero state on said D+ and D−

serial bus connections.

3. The bridge of claim 2, further comprising a D+ data transmit driver connected to said D+ serial bus connection and a D−

data transmit driver connected to said D−

serial bus connection, wherein said serial bus disconnect circuit provides for a single-ended zero state by driving said D+ data transmit driver to a low state while said D−

data transmit driver is either in a high-impedance state or a low state.

4. The bridge of claim 2, wherein said serial bus disconnect circuit comprises a buffer having an input tied to said peripheral-device-ready signal parallel bus connection, said bridge further comprising a pull-up resistance R_P, having an effective value of 1.5 kΩ

±

5%, connected between said D+ serial bus connection and the output of said buffer, wherein said serial bus disconnect circuit provides for a single-ended zero state by driving the output of said buffer to either a high-impedance state or a low state.

5. The bridge of claim 2, wherein said bridge is powered from its serial bus connection.

6. The bridge of claim 2, wherein said bridge is self-powered.

7. The bridge of claim 2, wherein said bridge is configured for attachment between the external parallel port of a peripheral and an external Universal Serial Bus port of a host.

8. The bridge of claim 2, wherein said bridge is integrated into a host system.

9. The bridge of claim 2, wherein said bridge further comprises a bridging logic circuit having a reset, wherein said serial bus disconnect circuit is tied to said reset so as to hold said bridging logic circuit in a reset state while providing for a single-ended zero state on said D+ and D−

serial bus connections.

10. The bridge of claim 9, wherein when said bridging logic is in said reset state, said bridging logic provides for a single-ended zero state on said D+ and D−

serial bus connections.

11. A Universal Serial Bus to IEEE-1284-1994 compliant parallel bus bridge comprising:

a Universal Serial Bus port having a D+ connection, a D−

connection, a V_bus connection, and a serial bus ground connection;

an IEEE-1284-1994 compliant parallel port having a Peripheral Logic High signal connection; and

a serial bus disconnect circuit tied to said Peripheral Logic High signal connection, said serial bus disconnect circuit responding to a floating condition or a deassert signal appearing at said Peripheral Logic High signal connection by providing for a single-ended zero state on said D+ and D−

connections.

12. The bridge of claim 11, further comprising a D+ data transmit driver connected to said D+ connection and a D−

data transmit driver connected to said D−

connection, wherein said serial bus disconnect circuit provides for a single-ended zero state by driving said D+ data transmit driver to a low state while said D−

data transmit driver is either in a high-impedance state or a low state.

13. The bridge of claim 11, wherein said serial bus disconnect circuit comprises a buffer having an input connected to said Peripheral Logic High signal connection and an output connected through a resistance of 1.5 kΩ

±

5% to said D+ connection, wherein when said bridge is powered, a floating condition or a low condition at said Peripheral Logic High signal connection produces either a high impedance or a low state at said buffer output.

14. A method of operating a powered bridge between a Universal Serial Bus host and an IEEE-1284-1994 peripheral, said method comprising the steps of:

indicating a device connect condition to said Universal Serial Bus host when said peripheral asserts its IEEE-1284-1994 Peripheral Logic High signal; and

indicating a device disconnect condition to said Universal Serial Bus host when said peripheral deasserts or floats its IEEE-1284-1994 Peripheral Logic High signal, or when said peripheral is physically disconnected from said bridge.

15. The method of claim 14, wherein said indicating a device connect condition step comprises connecting a 3.3 V ±

0.3 V supply to the D+ Universal Serial Bus line through a 1.5 kΩ

±

5% resistance when said peripheral'"'"'s Peripheral Logic High signal is asserted.

16. The method of claim 14, wherein said indicating a device connect condition step comprises connecting said peripheral'"'"'s Peripheral Logic High signal to both the D+ Universal Serial bus line and to the Universal Serial Bus ground through a resistive voltage divider circuit that approximates a 1.5 kΩ

impedance tied to a 3.3 V supply when said Peripheral Logic High signal is asserted.

17. The method of claim 14, wherein said indicating a device disconnect condition step comprises increasing the resistance between a 3.3 V ±

0.3 V supply and the D+ Universal Serial Bus line to a value significantly greater than 15 kΩ

when said Peripheral Logic High signal is deasserted or floating.

18. The method of claim 14, wherein said indicating a device connect condition and indicating a device disconnect condition steps comprise buffering said peripheral'"'"'s Peripheral Logic High signal with a buffer producing a 3.3 V ±

0.3 V output for a 5 V input signal, and referencing a pull-up resistor to said buffer output, where said pull-up resistor is connected to the D+ bridge connection to the Universal Serial Bus.

19. The method of claim 14, wherein said bridge comprises a bridging logic circuit, further comprising the step of holding said bridging logic circuit in a reset state when said peripheral'"'"'s Peripheral Logic High signal is either deasserted or floating.