Computer system with improved memory access

• US 6,279,065 B1
• Filed: 06/03/1998
• Issued: 08/21/2001
• Est. Priority Date: 06/03/1998
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Chin, Kenneth T., Collins, Michael J., Jones, Phillip M., Johnson, Jerome J., Piccirillo, Gary J., Lester, Robert A., Coffee, C. Kevin
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): SCHUSTER, KATHARINA W
• Application Number:
  US09/090,271
• Time in Patent Office: 1,175 Days
• Field of Search: 395/821, 710/129, 710/128, 710/57, 710/68, 710/107, 709/227, 709/238, 711/101, 711/104, 711/105, 711/149, 711/151, 711/155, 711/154, 711/158, 711/167, 370/428
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.

Claims

1. A computer system, comprising:

a CPU;

a system main memory; and

an interface coupling said CPU and said main memory, said interface apparatus including;

a memory controller that connects to said main memory and which controls write transactions to the memory device; and

a CPU interface coupled to said memory controller, said CPU interface being capable of initiating a write transaction to said main memory before all of the data to be written is available to the memory controller.

2. A computer system as in claim 1 wherein said interface apparatus further includes a data queue coupled between said CPU interface and said memory controller.

3. A computer system as in claim 2 wherein said data queue includes a plurality of multi-byte storage rows for storing data to be written to said memory device by said CPU.

4. A computer system as in claim 3 wherein each of said multi-byte storage rows is capable of storing four quad words.

5. A computer system as in claim 4 wherein said interface initiates a write transaction to said main memory once a first of said plurality of quad words is stored in said data queue and before the remaining quad words are stored in said data queue.

6. A computer system as in claim 5 wherein said interface also includes control logic operatively coupled to said data queue and to said CPU interface, and wherein said CPU interface initiates said memory write cycle by asserting a control signal to said control logic.

7. A computer system as in claim 6 wherein said control logic asserts a request signal to said memory controller when said CPU interface asserts said control signal.

8. A computer system as in claim 7 wherein said main memory comprises a synchronous dynamic random access memory (SDRAM).

9. A computer system as in claim 8 wherein said memory controller initiates an activate command to said SDRAM upon receipt of said request signal.

10. A computer system as in claim 1 wherein said interface includes an expansion bus interface and said computer system includes an expansion bus coupled to said expansion bus interface, said expansion bus capable of providing data to be written to said main memory.

11. A computer system as in claim 10 wherein said interface includes a data queue coupled between said expansion bus interface and said memory controller, said data queue including a plurality of multi-byte storage rows for storing data to be written to said memory device by said expansion bus.

12. A computer system as in claim 11 wherein each of said multi-byte storage rows is capable of storing four quad words.

13. A computer system as in claim 12 wherein said interface initiates a write transaction to said memory device once a first of said plurality of quad words is stored in said data queue and before the remaining quad words are stored in said data queue.

14. A computer system as in claim 13 wherein said interface also includes control logic operatively coupled to said data queue and to said expansion bus interface, said expansion bus interface initiates said memory write cycles by asserting a control signal to said control logic which then asserts a request signal to said memory controller.

15. A computer system comprising:

a CPU;

a main memory device capable of storing data; and

an interface coupling said CPU and said main memory device, said interface including;

a memory controller that connects to said main memory device and which controls write transactions to the main memory device;

a CPU interface coupled to said memory controller, said CPU interface being capable of initiating a write transaction before all of the data to be written is available to the memory controller;

a CPU-to-memory data queue coupled to said CPU interface and said memory controller for temporarily storing a plurality of data portions to be written to the main memory device;

said CPU interface capable of initiating a write transaction to the main memory device before all of said data portions are stored in said CPU-to-memory data queue.

16. A computer system as in claim 15 wherein said interface further includes a CPU to memory address queue which temporarily stores a plurality of memory addresses associated with said plurality of data portions stored in said data queue.

17. A computer system as in claim 15 wherein said computer system includes an expansion bus capable of providing data to be written to said memory device and said interface includes an expansion bus interface coupled to said expansion bus.

18. A computer system as in claim 17 wherein said interface also includes an expansion bus-to-memory data queue for temporarily storing a plurality of data portions to be written to said main memory device and said expansion bus interface is capable of initiating a write transaction to the memory device before all of said data portions are stored in said expansion bus-to-memory data queue.