Method and apparatus for significantly improving the reliability of multilevel memory architecture

• US 6,279,133 B1
• Filed: 10/05/1998
• Issued: 08/21/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Fees

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Rostoker, Michael D., Vafai, Manouchehr
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US09/166,500
• Time in Patent Office: 1,051 Days
• Field of Search: 714/758, 714/752, 714/763, 714/764, 714/800, 714/802, 714/804, 714/807, 714/757, 714/766, 714/718, 341/50, 341/62, 341/104, 341/105, 365/189.01
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Method and apparatus for significantly improving the reliability of multilevel (MLT) memory architecture. Before writing to MLT architecture, each MLT word is encoded into a coded bit stream in such a way that the resultant coded data contains the original word plus additional digits which are a function of the content of memory. During the reading of the memory, the stored data is decoded, and takes advantage of redundancy to correct and eliminate errors introduced during read and write operations of the MLT architecture. The invention is useful for systems such as general-purpose computers (PCs, workstations, etc.), telecommunications devices (telephones—wired and wireless, switches, hubs, routers, etc.), audio and visual devices (recording and playback, editing, format switching, compression, etc.), vehicles (automobiles, aircraft, trains, boats, satellites, spacecraft, etc.). Systems and subsystems may be incorporated on a single integrated circuit (IC) die having MLT RAM or enhanced MLT memory. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Claims

1. Multilevel memory architecture, comprising:

an array of storage cells, each cell capable of holding a number greater than two distinct states;

means for encoding data into the number of states;

means for providing the encoded data to the storage cells as stored data;

means for accessing the stored data from the storage cells; and

means for decoding the stored data.

2. Multilevel memory architecture, according to claim 1, further comprising:

a temporary storage device disposed between the means for encoding data and the array of storage cells.

3. Multilevel memory architecture, according to claim 2, wherein:

the temporary storage device is a FIFO.

4. Multilevel memory architecture, according to claim 1, further comprising:

a temporary storage device disposed between the means for accessing the stored data and the array of storage cells.

5. Multilevel memory architecture, according to claim 4, wherein:

the temporary storage device is a FIFO.

6. Multilevel memory architecture, according to claim 1, further comprising:

a first temporary storage device disposed between the means for encoding data and the array of storage cells; and

a second temporary storage device disposed between the means for accessing the stored data and the array of storage cells.

7. Method of operating a multilevel memory, comprising:

before writing to memory, encoding each MLT word into a coded bit stream so that the resultant coded data contains the original word plus additional redundant digits which are a function of the content of memory; and

writing the resultant coded data to memory as stored data.

8. Method, according to claim 7, further comprising:

during a read cycle, decoding the stored data.

9. Method, according to claim 8, further comprising:

during the read cycle, applying redundancy techniques to correcting and eliminating errors.

10. Method, according to claim 8, further comprising:

during the read cycle and before decoding the stored data, writing the stored data to a temporary storage device.

11. Method, according to claim 7, further comprising:

before writing to memory and before encoding, writing block data to a temporary storage device.

12. Method of operating a multilevel memory, comprising:

before writing to memory, encoding each MLT word into a coded bit stream so that the resultant coded data contains the original word plus additional redundant digits which are a function of the content of memory;

writing the resultant coded data to memory as stored data;

during a read cycle, decoding the stored data;

during the read cycle and before decoding the stored data, writing the stored data to a temporary storage device; and

before writing to memory and before encoding, writing block data to a temporary storage device.

13. Method, according to claim 12, further comprising:

during the read cycle, applying redundancy techniques to correcting and eliminating errors.

14. An electronic system incorporating at least one integrated circuit (IC) chip, said IC chip comprising:

an array of storage cells, each cell capable of holding a number greater than two distinct states;

means for encoding data into the number of states;

means for providing the encoded data to the storage cells;

means for accessing the stored data; and

means for decoding the stored data.

15. An electronic system, according to claim 14, wherein:

the electronic system is selected from the group consisting of general-purpose computer, telecommunication device, network device, consumer device, receiver, recorder, display device, and vehicle.