Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices

• US 6,281,078 B1
• Filed: 12/18/1997
• Issued: 08/28/2001
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Au, Ken, Chang, Kent Kuohua, He, Yuesong, Wang, John Jianshi
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): KIELIN, ERIK J
• Application Number:
  US08/993,344
• Time in Patent Office: 1,349 Days
• Field of Search: 438/257-266, 438/593, 438/304, 438/596, 438/267, 438/657
• US Class Current: 438/261
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.

Claims

1. A method for fabricating a semiconductor device comprising:

providing a first layer of polysilicon on the surface of a semiconductor substrate;

protecting selected portions of said first layer of polysilicon and exposing portions of said first layer of polysilicon by providing a masking material over said selected portions;

removing said exposed portions of said first layer of polysilicon;

providing a second layer of polysilicon over said surface of said semiconductor substrate;

anisotropically removing said second layer of polysilicon, so as to form spacers of said second layer of polysilicon adjacent said protected selected portions of said first layer of polysilicon;

removing said masking material;

providing a triple layer of oxide-nitride-oxide (ONO) over said first layer of polysilicon and said spacer;

forming a third layer of polysilicon over said triple layer of oxide-nitride-oxide;

removing portions of said third layer of polysilicon, said triple layer, said first layer of polysilicon and said spacer between intended locations of memory core cells successively; and

removing ONO material remaining between intended locations of memory core cells.

2. The method of claim 1 wherein the step of removing said triple layer comprises using a mixture of H₂O and HF liquids.

3. The method of claim 2 wherein a ratio of the mixture of H₂O to HF is approximately 100 to 1.

4. The method of claim 2 wherein a duration of exposing is approximately 60 seconds.

5. A method for fabricating a semiconductor device comprising:

providing a first insulating layer over a semiconductor substrate;

forming a first conductive layer over said first insulating layer;

forming a mask over said first conductive layer thereby protecting selected portions of said first conductive layer and exposing remaining portions of said first conductive layer;

removing exposed remaining portions of said first conductive layer;

providing a second conductive layer over said semiconductor substrate, including said protected selected portions of said first conductive layer; and

anisotropically removing said second conductive layer so as to form spacers of said second conductive layer adjacent said selected protected portions of said first conductive layer.

6. The method of claim 5, wherein said first insulating layer comprises tunnel oxide.

7. The method of claim 5, wherein said first conductive layer comprises amorphous silicon.

8. The method of claim 5, wherein said forming a mask comprises:

forming a mask layer over said first conductive layer;

depositing and patterning a photoresist layer over said mask layer to expose a portion of said mask layer; and

removing said exposed portion of said mask layer to form said mask.

9. The method of claim 8, further comprising removing said photoresist layer.

10. The method of claim 5, wherein said mask comprises oxide.

11. The method of claim 5, further comprising forming said mask over an active region of said substrate.

12. The method of claim 5, wherein said portion of said first conductive layer comprises a portion above a core region of a field oxide region in said substrate.

13. The method of claim 5, wherein said second conductive layer comprises amorphous silicon.

14. The method of claim 5, further comprising:

removing said mask; and

forming a dielectric layer over said first insulating layer, said spacer and said protected selected portion of said first conductive layer.

15. The method of claim 14, wherein said dielectric layer comprises ONO (oxide-nitride-oxide).

16. The method of claim 14, further comprising:

forming a second conductive layer over said dielectric layer; and

selectively removing portions of said second conductive layer, said dielectric layer, said first conductive layer and said spacer, thereby forming said semiconductor device.

17. The method of claim 16, further comprising removing, after said selectively removing, portions of said dielectric layer not covered by said second conductive layer.

18. The method of claim 17, wherein said removing portions of said dielectric layer comprises exposing said semiconductor device to a hydrogen fluoride solution.

19. The method of claim 17, wherein said removing portions of said dielectric layer comprises performing a buffer oxide etch.

20. The method of claim 15, further comprising cleaning said semiconductor device.

21. The method of claim 20, further comprising removing any polystringers.

22. The method of claim 21, wherein said removing any polystringers comprises oxidizing said polystringers.

23. The method of claim 22, further comprising heating said semiconductor device to oxidize said polystringers.

24. The method of claim 14, further comprising:

forming a tungsten silicide layer over said second conductive layer; and

forming a silicon oxy-nitride (SiON) layer over said tungsten silicide layer.