Method for fabricating an embedded flash memory cell

• US 6,281,089 B1
• Filed: 09/14/1999
• Issued: 08/28/2001
• Est. Priority Date: 09/14/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Worldwide Semiconductor Manufacturing Corp. (Taiwan Semiconductor Manufacturing Company Limited)
• Inventors: Chen, Chih Ming
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/395,188
• Time in Patent Office: 714 Days
• Field of Search: 438/315, 438/257-67, 438/225, 438/297, 438/142, 438/309, 257/304-308, 257/300-303
• US Class Current: 438/315
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for embedded flash cell fabrication beyond 0.35 Ξm generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxide window and capacitor coupling area. Next, a conventional photolithogrpahy and etching method is used to formed a patterned photoresist on the substrate and expose flash cell areas. Then N-type conductive dopants are implanted into the substrate. For 0.35 μm generation, the concentration of dopant is increased to 5El7˜1El9 atoms/cm³. Next, the patterned photoresist layer are removed and thicker tunnel oxide and thinner gate oxide layer are formed in one processing step. Next, a doped polysilicon layer is deposited by using a conventional chemical vapor deposition over the tunnel oxide layer to serve as the floating gate of the flash cell.

Claims

1. A method for an embedded flash cell fabrication under 0.35 μ

m generation, said method comprising;

providing a semiconductor substrate;

forming an isolation region on said semiconductor substrate to separate a first active area and a second active area;

doping impurity into said first active area with a concentration more than 5E17 atoms/cm³;

forming a tunnel oxide layer on said first active area and a gate oxide layer on said second active area simultaneously; and

forming a conductive layer on said tunnel oxide layer.

2. The method of claim 1, wherein said isolation region is a field oxide layer.

3. The method of claim 1, wherein said impurity consists of arsenic ion and phosphorous ion.

4. The method of claim 1, wherein said forming said tunnel oxide and said gate oxide step use dry oxidation.

5. The method of claim 4, wherein said dry oxidation use oxygen (O₂) oxidant.

6. The method of claim 1, wherein said tunnel oxide layer has a thickness between about 90 to 100 angstroms.

7. The method of claim 1, wherein said forming said conductive layer step use chemical vapor deposition (CVD).

8. The method of claim 1, wherein said conductive layer is a doped polysilicon layer.

9. A method for an embedded flash cell fabrication under 0.35 μ

m generation, said method comprising;

providing a semiconductor substrate;

patterning a pad oxide layer and a silicon nitride layer which are formed sequentially on said semiconductor substrate;

forming an isolation region to separate a first active area and a second active area;

patterning a photoresist on said semiconductor substrate to expose said first active area;

doping impurity into said first active area with a concentration more than 5E17 atoms/cm³;

forming a tunnel oxide layer on said first active area and a gate oxide layer on said second active area simultaneously; and

forming a doped polysilicon layer on said tunnel oxide layer.

10. The method of claim 9, wherein said isolation region is a field oxide layer.

11. The method of claim 9, wherein said impurity consists of arsenic ion and phosphorous ion.

12. The method of claim 9, wherein after said doping step further comprises the step of removing said pad oxide.

13. The method of claim 12, wherein said pad oxide is removed by diluted hydrofluoric acid (HF) solution.

14. The method of claim 9, wherein said forming said tunnel oxide and said gate oxide step use dry oxidation.

15. The method of claim 14, wherein said dry oxidation use oxygen (O₂) oxidant.

16. The method of claim 9, wherein said tunnel oxide layer has a thickness between about 90 to 100 angstroms.

17. The method of claim 9, wherein said forming said doped polysilicon layer step use chemical vapor deposition (CVD).

18. The method of claim 9, wherein said doped polysilicon layer act as floating gate of said flash cell.