Method for fabricating an embedded flash memory cell
First Claim
1. A method for an embedded flash cell fabrication under 0.35 μ
- m generation, said method comprising;
providing a semiconductor substrate;
forming an isolation region on said semiconductor substrate to separate a first active area and a second active area;
doping impurity into said first active area with a concentration more than 5E17 atoms/cm3;
forming a tunnel oxide layer on said first active area and a gate oxide layer on said second active area simultaneously; and
forming a conductive layer on said tunnel oxide layer.
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Abstract
A method for embedded flash cell fabrication beyond 0.35 Ξm generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxide window and capacitor coupling area. Next, a conventional photolithogrpahy and etching method is used to formed a patterned photoresist on the substrate and expose flash cell areas. Then N-type conductive dopants are implanted into the substrate. For 0.35 μm generation, the concentration of dopant is increased to 5El7˜1El9 atoms/cm3. Next, the patterned photoresist layer are removed and thicker tunnel oxide and thinner gate oxide layer are formed in one processing step. Next, a doped polysilicon layer is deposited by using a conventional chemical vapor deposition over the tunnel oxide layer to serve as the floating gate of the flash cell.
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Citations
18 Claims
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1. A method for an embedded flash cell fabrication under 0.35 μ
- m generation, said method comprising;
providing a semiconductor substrate;
forming an isolation region on said semiconductor substrate to separate a first active area and a second active area;
doping impurity into said first active area with a concentration more than 5E17 atoms/cm3;
forming a tunnel oxide layer on said first active area and a gate oxide layer on said second active area simultaneously; and
forming a conductive layer on said tunnel oxide layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- m generation, said method comprising;
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9. A method for an embedded flash cell fabrication under 0.35 μ
- m generation, said method comprising;
providing a semiconductor substrate;
patterning a pad oxide layer and a silicon nitride layer which are formed sequentially on said semiconductor substrate;
forming an isolation region to separate a first active area and a second active area;
patterning a photoresist on said semiconductor substrate to expose said first active area;
doping impurity into said first active area with a concentration more than 5E17 atoms/cm3;
forming a tunnel oxide layer on said first active area and a gate oxide layer on said second active area simultaneously; and
forming a doped polysilicon layer on said tunnel oxide layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
- m generation, said method comprising;
Specification