Cobalt silicide structure for improving gate oxide integrity and method for fabricating same

• US 6,281,102 B1
• Filed: 01/13/2000
• Issued: 08/28/2001
• Est. Priority Date: 01/13/2000
• Status: Expired due to Fees

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Lee, Shih-Ked, Lee, Sang-Yun, Lo, Guo-Qiang, Cao, Wanqing
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/484,580
• Time in Patent Office: 593 Days
• Field of Search: 438/143, 438/180, 438/402, 438/476, 438/592, 438/630, 438/636, 438/655-656, 438/664, 438/683, 438/299, 438/300, 438/301, 438/564, 438/672, 438/692, 438/660, 438/663
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide). Consequently, an underlying gate oxide or substrate is advantageously protected from the effects of cobalt silicide spiking.

Claims

1. A method of forming a cobalt salicide structure, the method comprising the steps of:

forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure;

loading the silicon structure into a chamber;

introducing a vacuum to the chamber;

then

depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide;

depositing a cobalt layer over the titanium layer;

depositing an oxygen impervious cap layer over the cobalt layer; and

then

breaking the vacuum in the chamber; and

annealing the silicon structure, the titanium layer, the cobalt layer and the cap layer, thereby forming the cobalt salicide structure.

2. The method of claim 1, wherein the cap layer comprises titanium or titanium nitride.

3. The method of claim 1, wherein the aneal is a rapid thermal anneal (RTA).

4. The method of claim 1, wherein the cobalt salicide structure has a minimum feature size less than 0.25 microns.

5. The method of claim 1, wherein the silicon structure comprises conductively doped polysilicon.

6. The method of claim 1, wherein the titanium layer is deposited to a thickness in the range of 2 to 5 nm.

7. The method of claim 1, wherein the cobalt layer is deposited to a thickness in the range of 5 to 20 nm.

8. The method of claim 1, wherein the cobalt salicide structure forms a gate electrode of a transistor.

9. The method of claim 1, wherein the cobalt salicide structure forms a portion of a source region of a transistor.

10. The method of claim 1, wherein the anneal is performed at a temperature in the range of 450 to 550°

C.

11. A method of forming a cobalt salicide structure, the method comprising the steps of:

forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure;

loading the silicon structure into a chamber;

introducing a vacuum to the chamber;

then

depositing a titanium layer to a thickness in the range of 2 to 5 nm over the first surface of the silicon structure;

depositing a cobalt layer over the titanium layer;

depositing an oxygen impervious cap layer over the cobalt layer; and

then

breaking the vacuum in the chamber; and

annealing the silicon structure, the titanium layer, the cobalt layer and the cap layer, thereby forming the cobalt salicide structure, wherein the titanium layer prevents the cobalt layer from diffusing at interfaces of the cobalt layer and the silicon structure.

12. The method of claim 11, wherein the cap layer comprises titanium or titanium nitride.

13. The method of claim 11, wherein the anneal is a rapid thermal anneal (RTA).

14. The method of claim 11, wherein the cobalt salicide structure has a minimum feature size less than 0.25 microns.

15. The method of claim 11, wherein the silicon structure comprises conductively doped polysilicon.

16. The method of claim 11, wherein the cobalt layer is deposited to a thickness in the range of 5 to 20 nm.

17. The method of claim 11, wherein the cobalt salicide structure forms a gate electrode of a transistor.

18. The method of claim 11, wherein the cobalt salicide structure forms a portion of a source region of a transistor.

19. The method of claim 11, wherein the anneal is performed at a temperature in the range of 450 to 550°

C.