Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask

• US 6,281,547 B1
• Filed: 05/08/1997
• Issued: 08/28/2001
• Est. Priority Date: 05/08/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/853,150
• Time in Patent Office: 1,573 Days
• Field of Search: 257/330-334, 257/135, 257/401, 438/270-274
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention discloses a DMOS transistor cell, supported on a substrate of a first conductivity type. The DMOS transistor cell includes a body region of a second conductivity type disposed in the substrate defining a central portion of the cell. This DMOS transistor cell further includes a trench gate filled with polysilicon therein surrounding the body region and defining a boundary of the cell. This DMOS transistor cell further includes a source of the first conductivity type defined by a narrow strip of source region disposed in the body region along an edge thereof adjacent to the trench gate. This transistor cell further includes a source contact defined by a cross-shaped trench filled with polysilicon disposed in the body region and a trench edge source extension extending laterally between the narrow strip of source region and in electric contact thereto for providing area for electrically connecting to a source contact to be formed thereon whereby the source contact can be more conveniently manufactured provided with reliable good contact to the narrow strip of source region while achieving cost savings without requiring the use of a source mask.

Claims

1. A DMOS transistor cell, supported on a substrate of a first conductivity type, comprising:

a body region of a second conductivity type disposed in said substrate defining a central portion of said cell;

a trench gate filled with polysilicon therein surrounding said body region and defining a boundary of said cell;

a source of said first conductivity type defined by a narrow strip of source region disposed along an edge of said trench gate thus said narrow strip of said source region constituting an outer boundary surrounding said body region;

said body region further comprising a cross-shaped trench filled with polysilicon horizontally extended to said source region near said outer boundary surrounding said body region; and

a source contact region constituting a narrow strip region of said first conductivity type along said cross shaped trench and in electrical contact with said source region.

2. The DMOS transistor cell of claim 1 further comprising:

an insulating layer covering said transistor cell having a contact window opened above said source contact with contact metal filled therein for contacting said source contact and electrically connected to said source region therefrom.

3. The DMOS transistor cell of claim 1 wherein:

said narrow strip of source region having a width ranging from 0.2 to 0.8 μ

m and said cross-shaped trench having a trench width ranging from 0.5 to 2.0 μ

m whereby a transistor cell of narrow source is provided with improved ruggedness while maintaining reliable source contact connected by said source contact along said cross-shaped trench extended to said source region.

4. The DMOS transistor cell of claim 1 wherein:

said substrate of a first conductivity type is a N-type conductivity substrate and said body region of a second conductivity type is a P-type conductivity body.

5. The DMOS transistor cell of claim 1 wherein:

said substrate of a first conductivity type is a P-type conductivity substrate and said body region of a second conductivity type is a N-type conductivity body.

6. A power transistor cell, supported on a semiconductor substrate, comprising:

a body region disposed in said substrate defining a central portion of said cell;

a trench gate filled with conductive material therein surrounding said body region and defining a boundary of said cell;

a source region disposed along an edge of said trench gate thus constituting a narrow strip of source region constituting an outer boundary surrounding said body region;

said body region further comprising a horizontally-extended elongated source contact trench filled with a conductive material therein extended horizontally to said source region; and

a source contact disposed along an horizontal edge of said source contact trench thus extended horizontally to and in electrical contact with said source region for providing a more reliable source connection thereto.

7. The power transistor cell of claim 6 further comprising:

an insulating layer covering said transistor cell having a contact window opened above said source contact with contact metal filled therein for contacting said source contact and electrically connected to said source region therefrom.

8. The power transistor cell of claim 6 wherein:

said source region having a width ranging from 0.2 to 0.8 μ

m and said cross-shaped trench having a trench width ranging from 0.5 to 2.0 μ

m whereby a transistor cell of narrow source is provided with improved ruggedness while maintaining reliable source contact connected by said source contact along said cross-shaped trench extended to said source region.

9. The power transistor cell of claim 6 wherein:

said substrate being a first conductivity type is a N-type conductivity substrate and said body region being a second conductivity type is a P-type conductivity body.

10. The power transistor cell of claim 6 wherein:

said substrate being a first conductivity type is a P-type conductivity substrate and said body region being a second conductivity type is a N-type conductivity body.