Method and test circuit for developing integrated circuit fabrication processes

• US 6,281,696 B1
• Filed: 08/24/1998
• Issued: 08/28/2001
• Est. Priority Date: 08/24/1998
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Voogel, Martin L.
• Primary Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US09/139,629
• Time in Patent Office: 1,100 Days
• Field of Search: 324/763, 324/765, 324/500, 324/158.1, 324/73.1
• US Class Current: 324/762.03
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

During the development of process parameters for fabricating an integrated circuit, a test circuit is provided on the wafer that provides rapid identification of process problems (i.e., before failure analysis), detects defects down to a part-per-million (PPM) level, and identifies the precise location of any defects, thereby facilitating rapid failure analysis during the development and refinement of IC fabrication processes used to fabricate an integrated circuit (IC). In a first embodiment, the test circuit includes parallel conductive paths that are selectively connected to a signal source by pass transistors. Open circuits are identified by sequentially connecting one end of the conductive paths to the signal source and measuring the current at the other end. In a second embodiment, the test circuit includes perpendicular sets of overlapping conductors. Short conductive segments extend in parallel with a first set of conductors that are electrically connected to a second set of conductors. Short circuits are identified by sequentially connecting the first conductive paths to the signal source and measuring the current generated in the second conductive paths. In a third embodiment, the test circuit includes perpendicular sets of overlapping conductors. Pairs of parallel first conductors are selectively connected by bypass circuits. The location of breaks in the first conductors is identified by systematically bypassing sections of the first conductors, thereby facilitating failure analysis.

Claims

1. A test circuit for identifying defects arising during process steps performed during the fabrication of an integrated circuit on a semiconductor wafer, the test circuit comprising:

a first terminal;

a second terminal;

a plurality of first conductive paths connected in parallel; and

a first switching circuit for selectively connecting one of the plurality of first conductive paths between the first terminal and the second terminal,

wherein a first path of the plurality of first conductive paths is formed during a first process step, and

wherein a second path of the plurality of first conductive paths is formed during a second process step, the second process step being performed after the first process step.

2. The test circuit according to claim 1, further comprising:

a third terminal;

a fourth terminal;

a plurality of second conductive paths connected in parallel, the plurality of second conductive paths extending across the plurality of first conductive paths such that the plurality of second conductive paths are electrically isolated from the plurality of first conductive paths;

a second switching circuit for selectively connecting one of the plurality of second conductive paths between the third terminal and the fourth terminal; and

a plurality of conductive segments, each conductive segment being located adjacent an associated one of the plurality of second conductive paths and being connected to an associated one of the plurality of first conductive paths.

3. The test circuit of claim 2 wherein the plurality of second conductive paths are formed from at least one of the following layers:

diffusion, metal, and polysilicon.

4. The test circuit of claim 1 wherein the plurality of first conductive paths and the plurality of second conductive paths are formed from different layers.

5. The test circuit according to claim 2, wherein each of the plurality of conductive segments extends parallel to an associated one of the plurality of second conductive paths, and is separated from the associated one of the plurality of first conductive paths by a distance determined by a design specification of the integrated circuit.

6. The test circuit according to claim 1, further comprising:

a third terminal;

a fourth terminal;

a plurality of second conductive paths connected in parallel, the plurality of second conductive paths extending across the plurality of first conductive paths such that the plurality of second conductive paths are electrically isolated from the plurality of first conductive paths;

a second switching circuit for selectively connecting one of the plurality of second conductive paths between the third terminal and the fourth terminal; and

a plurality of bypass circuits, each bypass circuit extending between an associated pair of paths of the plurality of first conductive paths and including a pass transistor having a gate controlled to selectively connect the associated pair of paths of the plurality of first conductors.

7. The test circuit according to claim 6, wherein the gate of each pass transistor is connected to the first switching circuit.

8. The test circuit of claim 1 wherein the plurality of first conductive paths are formed from at least one of the following layers:

diffusion, metal, and polysilicon.

9. The test circuit according to claim 1, wherein the first switching circuit comprises a plurality of pass transistors, each pass transistor being connected between the first terminal and a first end of an associated one of the plurality of first conductive paths, wherein each pass transistor includes a gate that is controlled by a decoder.

10. The test circuit according to claim 1, wherein one of the plurality of first conductive paths comprises first pieces of material formed in a first metal layer, second pieces of material formed in a second metal layer, and metal vias formed between associated first pieces and second pieces.

11. The test circuit according to claim 1, wherein one of the plurality of first conductive paths comprises diffusion regions linked by pieces of material formed in a first metal layer, each piece of material contacting portions of a surface of the semiconductor wafer that are respectively located over associated pairs of the diffusion regions.

12. The test circuit according to claim 1,

wherein the plurality of first conductive paths are arranged in a core region,

wherein the first switching circuit is located adjacent the core region, and

wherein the test circuit further comprises:

a decoder for receiving an address signal, and for causing a selected switch of the first switching circuit to turn on to connect a selected one of the plurality of first conductive paths to the first terminal in response to the address signal; and

a control circuit for receiving a mode control signal, and for selectively configuring the test circuit by connecting the first terminal to an external voltage source or an external sense amplifier.