Low voltage differential signaling driver with pre-emphasis circuit

• US 6,281,715 B1
• Filed: 09/29/1999
• Issued: 08/28/2001
• Est. Priority Date: 04/29/1998
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: DeClue, Larry W., Chow, James, Wen, Kenny
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/408,773
• Time in Patent Office: 699 Days
• Field of Search: 327/63-66, 327/68, 327/69, 327/76, 327/85, 327/51-53, 327/108, 326/83, 326/86
• US Class Current: 327/65
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834

Abstract

A low voltage differential signaling (“LVDS”) line driver includes a pre-emphasis circuit to increase the drive capability of the LVDS line driver. A current source provides a first drive current to a current steering circuit. The pre-emphasis circuit includes a second current source, a current sourcing circuit coupled to the second current source and the current steering circuit and a current sinking circuit coupled to the second current source and the current steering circuit. In this way, first and second drive currents are provided to during the switching of the signal states of an input signal, so that more drive current is supplied to the output of the LVDS line driver circuit. Thus, the time it takes for the current steering circuit to switch the drive current between the first and second directions is decreased.

Claims

1. A line driver circuit that provides a differential signal to an external circuit, the line driver circuit comprising:

a current steering circuit;

a current source coupled to the current steering circuit and configured to provide a first drive current to the current steering circuit;

a pre-emphasis circuit coupled to the current steering circuit and configured to receive an input signal switching between first and second signal states, and in accordance therewith provide a second drive current during a transition time beginning when the input signal switches between first and second signal states for a first time and ending before the input signal switches between first and second signal states for a second time; and

first and second output nodes configured to couple to an external circuit and convey third and fourth drive currents, wherein

the current steering circuit is configured to receive the input signal and in accordance therewith direct the first and second drive currents in first and second directions, respectively, to provide the third and fourth drive currents, wherein the third and fourth drive currents together form at the first and second output nodes a differential output signal, and

wherein the pre-emphasis circuit includes

a current sinking circuit coupled to the current steering circuit;

a current sourcing circuit coupled to the current steering circuit, and

wherein during the transition time the current sourcing circuit pushes the second drive current into the current steering circuit and the current sinking circuit sinks a portion of a combination of the first and second drive currents from the current steering circuit, and

wherein the pre-emphasis circuit further includes

a logic circuit coupled to the current sinking circuit and the current sourcing circuit; and

a delay circuit coupled to the logic circuit and configured to receive the input signal and in accordance therewith generate a delayed input signal having first and second signal states, and wherein the logic circuit receives the input signal and the delayed input signal and in accordance therewith outputs a transition signal during the transition time, the transition time beginning when the input signal switches between first and second signal states and ending when the delayed input signal switches between first and second signal states.

2. The line driver circuit of claim 1, and wherein the delay circuit comprises a plurality of inverter circuits.

3. The line driver circuit of claim 1, and wherein the logic circuit comprises an exclusive-NOR circuit.

4. The line driver circuit of claim 1, and further comprising a bias circuit coupled to the current sourcing circuit and the current sinking circuit and configured to provide first and second bias signals to the current sourcing circuit and the current sinking circuit, respectively.

5. The line driver circuit of claim 1, and wherein the current sourcing circuit includes:

a first sourcing transistor coupled to the current steering circuit; and

a second sourcing transistor coupled to the first sourcing transistor and to a first supply voltage, and configured to receive a first bias signal, the current sinking circuit includes;

a first sinking transistor coupled to the current steering circuit; and

a second sinking transistor coupled to the first sinking transistor and to a second supply voltage, and configured to receive a second bias signal, the pre-emphasis circuit further includes;

a logic circuit coupled to the first sourcing transistor and the first sinking transistor; and

a delay circuit coupled to the logic circuit and configured to receive the input signal and in accordance therewith provide a delayed input signal having first and second signal states, and wherein

the logic circuit receives the input signal and the delayed input signal and in accordance therewith outputs a transition signal during the transition time corresponding to a time when both the input signal and the delayed input signal have the same signal states,

the first sourcing transistor receives the transition signal and in accordance therewith provides the second drive signal from the first supply voltage through the second sourcing transistor to the current steering circuit, and

the first sinking transistor receives the transition signal and in accordance therewith sinks the portion of the combination of the first and second drive currents from the current steering circuit through the second sinking transistor to the second supply voltage.

6. The line driver circuit of claim 1, and wherein the pre-emphasis circuit includes:

a current sourcing circuit coupled to the current steering circuit and to a first supply voltage;

a current sinking circuit coupled to the current steering circuit and to a second supply voltage;

an exclusive-NOR gate coupled to the current sinking circuit and to the current sourcing circuit; and

a delay circuit coupled to the exclusive-NOR gate and configured to receive the input signal and in accordance therewith generate a delayed input, wherein

the exclusive-NOR gate receives the input signal and the delayed input signal and in accordance therewith outputs a transition during the transition time, the transition time beginning when the input signal switches between first and second signal states and ending when the delayed input signal switches between first and second signal states,

the current sourcing circuit receives the transition signal and in accordance therewith conducts the second drive current from the first supply voltage to the current steering circuit, and

the current sinking circuit receives the transition signal and in accordance therewith conducts a portion of a combination of the first and second drive currents from the current steering circuit to the second supply voltage.

7. A method for increasing an output drive capability of a line driver circuit, the method comprising the steps of:

providing a first drive current to a current steering circuit;

receiving an input signal having first and second signal states and in accordance therewith outputting a transition signal during a transition time beginning when the input signal switches between first and second signal states for a first time and ending before the input signal switches between first and second signal states for a second time;

receiving the transition signal and in accordance therewith sourcing a second drive current into the current steering circuit and sinking a portion of a combination of the first and second drive currents from the current steering circuit during the transition time;

conveying third and fourth drive currents via first and second output nodes which are coupled to an external circuit; and

receiving the input signal by the current steering circuit and in accordance therewith directing the first and second drive currents in first and second directions to provide third and fourth drive currents, wherein the third and fourth drive currents together form at the first and second output nodes a differential output signal and wherein the first and second drive currents together provide an increased drive capability, and

wherein the step of receiving the transition signal and in accordance therewith sourcing a second drive current into the current steering circuit and sinking a portion of a combination of the first and second drive currents from the current steering circuit during the transition time includes;

receiving the transition signal by a current sourcing circuit and in accordance therewith pushing the second drive current from a voltage supply into the current steering circuit; and

receiving the transition signal by a current sinking circuit and in accordance therewith sinking the portion of the combination of the first and second drive currents to a circuit ground, and

wherein the step of receiving an input signal having first and second signal states and in accordance therewith outputting a transition signal during a transition time beginning when the input signal switches between first and second signal states for a first time and ending before the input signal switches between first and second signal states for a second time includes

delaying the input signal to generate a delayed input signal having first and second signal states;

receiving the input signal and the delayed input signal and in accordance therewith outputting a transition signal during the transition time corresponding to a time when both the input signal and the delayed input signal have the same signal state; and

receiving the transition signal and in accordance therewith pushing the second drive current into the current steering circuit during the transition time.

8. An apparatus including a line driver circuit, comprising:

a current steering circuit;

a current source coupled to the current steering circuit; and

a pre-emphasis circuit coupled to the current steering circuit, the pre-emphasis circuit comprising

a bias source,

a current sourcing circuit coupled to the bias source and connected directly to the current steering circuit, and

a current sinking circuit coupled to the bias source and the current steering circuit, and

wherein the pre-emphasis circuit further includes a logic circuit coupled to the current sourcing circuit and the current sinking circuit and a delay circuit coupled to the logic circuit.

9. The apparatus of claim 8, and wherein the delay circuit comprises a plurality of inverters.

10. The apparatus of claim 8, and wherein the logic circuit comprises an exclusive NOR gate.

11. The apparatus of claim 8, and wherein the current source and the current sourcing circuit couple to the current steering circuit at a first node, and the current sinking circuit couples to the current steering circuit at a second node.

12. The apparatus of claim 8, and wherein the current sourcing circuit and the current source couple to the current steering circuit at a common node.

13. The apparatus of claim 8, and wherein

the current source current couples to the current steering circuit at a first node,

the current sourcing circuit couples to the current steering circuit at second and third nodes, and

the current sinking circuit couples to the current steering circuit at the second and third nodes.

14. The apparatus of claim 13, and wherein the second and third nodes comprise receiving ends of a pair of transmission lines.

15. The apparatus of claim 13, and wherein the pre-emphasis circuit further comprises:

a logic circuit coupled to the current sourcing circuit and the current sinking circuit; and

a delay circuit coupled to the logic circuit.

16. The apparatus of claim 15, and wherein the logic circuit comprises:

an exclusive-NOR gate coupled to the delay circuit; and

a plurality of NOR gates coupled to the exclusive NOR gate, the current sourcing circuit and the current sinking circuit.

17. An apparatus including a line driver circuit, comprising:

a first current steering circuit;

a current source coupled to the first current steering circuit;

a second current steering circuit coupled to the first current steering circuit;

a current sourcing circuit coupled to the second current steering circuit; and

a bias source coupled to the current sourcing circuit, and

a current sinking circuit coupled to the second current steering circuit, and wherein

the current source current couples to the current steering circuit at a first node, and

the second current steering circuit couples to the first current steering circuit at second and third nodes.

18. The apparatus of claim 17, and wherein the second and third nodes comprise receiving ends of a pair of transmission lines.

19. The apparatus of claim 17, and further comprising:

a logic circuit coupled to the second current steering circuit; and

a delay circuit coupled to the logic circuit.

20. The apparatus of claim 19, and wherein the logic circuit comprises:

an exclusive-NOR gate coupled to the delay circuit; and

a plurality of NOR gates coupled to the exclusive NOR gate and the second current steering circuit.

21. A method for increasing an output drive capability of a line driver circuit, the method comprising:

receiving a first drive current for a first time period;

receiving a second drive current for a second time period, wherein the second time period and the first time period overlap;

steering the first drive current in first and second directions;

steering the second drive current in a same direction as the first drive current to provide an output signal proportional to a sum of the first and second drive currents; and

receiving an input signal having first and second input signal states;

delaying the input signal to generate a delayed input signal having first and second delayed signal states;

receiving the input signal and the delayed input signal and in accordance therewith outputting a transition signal during a first transition time when both the input signal and the delayed input signal have a same signal state; and

receiving the transition signal and in accordance therewith sourcing the second drive current during the first transition time.

22. The method of claim 21, and wherein the first time period is longer than the second time period.

23. The method of claim 21, and further comprising:

receiving a first input signal and in accordance therewith sourcing the first drive current; and

receiving a second input signal and in accordance therewith sourcing the second drive current.

24. The method of claim 21, and wherein the first transition time begins when the input signal switches between first and second input signal states and ends when the delayed input signal switches between the first and second delayed signal states.

25. The method of claim 21, and wherein the step of steering the first drive current comprises the step of:

receiving the input signal and in accordance therewith sourcing a first drive current during a second transition time, wherein the second transition time overlaps with the first transition time when both the input signal and the delayed input signal have a same signal state.

26. The method of claim of claim 25, and wherein the second transition time begins when the input signal switches from the first to the second input signal state and ends when the input signal switches from the second to the first input signal state.

27. An apparatus including a line driver circuit, comprising:

means for providing a first drive current;

means for providing a second drive current;

means for sourcing the second drive current for a first time period; and

means for receiving the second drive current during the first time period and the first drive current during a second time period, wherein the second time period and the first time period overlap, and in accordance therewith steering the first and second drive currents together in first and second directions to provide an output signal proportional to a sum of the first and second drive currents; and

means for sinking the first and second drive currents steered in first and second directions; and

wherein the means for receiving the second drive current during the first time period and the first drive current during a second time period includes;

means for receiving an input signal having first and second signal states and in accordance therewith providing a delayed input signal having delayed first and second signal states;

means for receiving the input signal and the delayed input signal and in accordance therewith generating a pre-emphasis signal during the first time period when the input signal and the delayed input signal have a same signal state;

means for receiving the pre-emphasis signal and in accordance therewith sourcing the second drive current from the means for providing a second drive current; and

means for steering the first and second drive currents together in first and second directions to provide the output signal proportional to the sum of the first and second drive currents.

28. The apparatus of claim 27, and wherein the means for steering comprises:

a first means for steering the first drive current in the first and second directions; and

a second means for steering the second drive current in the first and second directions.