SPST switch, SPDT switch, and communication apparatus using the SPDT switch

• US 6,281,762 B1
• Filed: 08/06/1999
• Issued: 08/28/2001
• Est. Priority Date: 10/07/1998
• Status: Expired due to Term

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Tanaka, Hiroaki, Sasabata, Akihiro, Nakao, Motoyasu
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): Jones, Stephen E.
• Application Number:
  US09/369,561
• Time in Patent Office: 753 Days
• Field of Search: 333/101, 333/103, 333/104, 333/262, 327/308, 327/283, 327/290, 327/268
• US Class Current: 333/103
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

An SPST switch having a small transmission loss and a small power consumption is provided. The drain and the source of an FET are connected to each other in series through an induction element and a capacitor element, one terminal of the capacitor element is connected to a first terminal, the other terminal is connected to a second terminal, the gate of the FET is connected to a control terminal, the capacitance of the capacitor element is made equal to the OFF capacitance of the FET, and the inductance of the induction element is set to be such a value that the induction element resonates at a signal frequency with the capacitor element.

Claims

1. A single pole single throw (SPST) switch, comprising:

a first, a second, and a control terminal;

a field effect transistor (FET) having a gate connected to the control terminal, a drain connected to the first terminal, and a source, the FET exhibiting an OFF capacitance from drain to source;

a capacitor element having a capacitance substantially equal to the OFF capacitance of the FET, the capacitor element having one end connected to the first terminal and another end connected to the second terminal; and

an induction element having one end connected to the source of the FET and another end connected to the second terminal, an inductance of the induction element being set such that it resonates with the capacitor element at a signal frequency.

2. A single pole double throw (SPDT) switch, comprising:

a first, a second, and a third terminal;

a first and a second control terminal;

a first field effect transistor (FET) having a gate connected to the first control terminal, a drain connected to the first terminal, and a source, the first FET exhibiting an OFF capacitance from drain to source;

a first capacitor element having a capacitance substantially equal to the OFF capacitance of the first FET, the capacitor element having one end connected to the first terminal and another end connected to the second terminal;

a first induction element having one end connected to the source of the first FET and another end connected to the second terminal, an inductance of the first induction element being set such that it resonates with the first capacitor element at a signal frequency

a second field effect transistor (FET) having a gate connected to the second control terminal, a drain connected to the first terminal, and a source, the second FET exhibiting an OFF capacitance from drain to source;

a second capacitor element having a capacitance substantially equal to the OFF capacitance of the second FET, the capacitor element having one end connected to the first terminal and another end connected to the third terminal; and

a second induction element having one end connected to the source of the second FET and another end connected to the third terminal, an inductance of the second induction element being set such that it resonates with the second capacitor element at a signal frequency.

3. A communication apparatus, comprising:

a single pole double throw (SPDT) switch, including;

a first, a second, and a third terminal;

a first and a second control terminal;

a first field effect transistor (FET) having a gate connected to the first control terminal, a drain connected to the first terminal, and a source, the first FET exhibiting an OFF capacitance from drain to source;

a first capacitor element having a capacitance substantially equal to the OFF capacitance of the first FET, the capacitor element having one end connected to the first terminal and another end connected to the second terminal;

a first induction element having one end connected to the source of the first FET and another end connected to the second terminal, an inductance of the first induction element being set such that it resonates with the first capacitor element at a signal frequency

a second field effect transistor (FET) having a gate connected to the second control terminal, a drain connected to the first terminal, and a source, the second FET exhibiting an OFF capacitance from drain to source;

a second capacitor element having a capacitance substantially equal to the OFF capacitance of the second FET, the capacitor element having one end connected to the first terminal and another end connected to the third terminal; and

a second induction element having one end connected to the source of the second FET and another end connected to the third terminal, an inductance of the second induction element being set such that it resonates with the second capacitor element at a signal frequency;

an antenna coupled to the first terminal;

a receiving circuit coupled to the second terminal;

a transmitting circuit coupled to the third terminal; and

a control circuit coupled to the first and second control terminals and being operable to provide switching signals to the first and second FETs such that the transmitting and receiving circuits are alternatively coupled to the antenna through the SPDT switch.