Pulse density modulator with improved pulse distribution

• US 6,281,822 B1
• Filed: 05/28/1999
• Issued: 08/28/2001
• Est. Priority Date: 05/28/1999
• Status: Expired due to Term

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.), Dot Wireless, Inc. (Texas Instruments, Inc.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.), Dot Wireless, Inc. (Texas Instruments, Inc.)
• Inventors: Park, Edwin C.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): PAIK, STEVEN SANGYUL
• Application Number:
  US09/322,539
• Time in Patent Office: 823 Days
• Field of Search: 341/53, 341/142, 341/144, 341/145, 341/152, 341/156
• US Class Current: 341/144
• CPC Class Codes: G06F 1/025 for functions having two-valued amplitude, e.g. Walsh functions
• CPC Class Codes: H03M 7/3006 Compensating for, or preventing of, undesired influence of physical parameters
• CPC Class Codes: H03M 7/3031 characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path

Abstract

A pulse density modulator generates output pulses that are optimized as to their even distribution over time. More particularly, the invention represents parallel or serial digital input signals as serial binary output signals, where the binary output pulses are evenly spaced over time to the greatest extent possible. The output signal includes a pattern that repeats during successive “cycles.” The number of pulses in each cycle varies in proportion to the magnitude of the digital input signal. When a digital input signal is provided to an accumulator, the accumulator repeatedly updates a current N-bit sum value by adding the digital input signal thereto. According to this computation, the accumulator either (1) provides a first prescribed signal on a carry output if the current sum cannot be expressed in N bits, or (2) provides a different prescribed signal on the carry output if the current sum can be expressed in N bits. The carry output provides a serial binary output having 2^N bits in each cycle. The accumulator may be used as a digital-to-analog converter by routing the carry output to an analog filter. Alternatively, the digital output of the accumulator may be used to provide a trigger signal of repeating, evenly spaced pulses.

Claims

1. A method of providing a serial binary output having pulses that are optimized as to their even distribution over time, comprising operations of:

receiving an input signal representing a current digital input value on an input line having N-bits;

providing the digital input signal as input to an accumulator configured to continually update a current N-bit sum by adding the input value thereto, and in response, the accumulator repeatedly;

updating the current sum by adding the digital input value thereto;

providing an output signal successively representing each current sum;

providing a first prescribed signal on an accumulator carry output if the current sum cannot be expressed in N bits, otherwise providing a different prescribed signal on the carry output if the current sum can be expressed in N bits;

disregarding the output signal;

directing signals on the carry output to circuitry external to the accumulator; and

the external circuitry allowing for up to N output pulses to be produced.

2. The method of claim 1, the input signal comprising a signal of multiple binary bits in parallel.

3. The method of claim 5, the operations further comprising:

during the repeated operations of the accumulator, sequentially providing multiple further digital input signals to the accumulator.

4. The method of claim 5, the operation of directing signals on the carry output to additional circuitry comprising:

providing signals on the carry output to an analog filter.

5. The method of claim 1, the additional circuitry comprising a processor and a logic “

OR”

gate, a trigger line comprising a hardware interrupt line coupling the processor and the logic “

OR”

gate, the logic “

OR”

gate having an input port for receiving the signals from the carry output and having an output port for providing the up to N output pulses.

6. A method of providing a serial binary output having pulses that are optimized as to their even distribution over time, comprising operations of:

receiving an input signal representing a current digital input value;

providing the digital input signal as input to an accumulator configured to continually update a current N-bit sum by adding the input value thereto, and in response, the accumulator repeatedly;

updating the current sum by adding the digital input value thereto;

providing an output signal successively representing each current sum;

providing a first prescribed signal on an accumulator carry output if the current sum cannot be expressed in N bits, otherwise providing a different prescribed signal on the carry output if the current sum can be expressed in N bits;

disregarding the output signal;

directing signals on the carry output to circuitry external to the accumulator;

the operation of receiving the input signal comprises receiving the input signal as a parallel, multi-bit binary signal on an input line having N bits;

the operations further comprise;

receiving a supplementary signal externally of the N-bit input line, the supplementary signal indicating an input signal having a value of 2^N; and

while the supplementary input signal is being received, continuously forcing the carry output to supply the first prescribed signal.

7. The method of claim 6, where:

the operations further comprise;

operating the accumulator to provide a sum signal representing the current sum upon a sum output; and

storing the sum signal in a register;

the operation of updating the current sum comprises operating the accumulator to add the digital input signal with the sum signal from the register.

8. The method of claim 6, the first prescribed signal being a binary one.

9. The method of claim 6, where:

the operation of receiving the input signal comprises receiving the input signal as a parallel, multi-bit binary signal on an input line having N bits.

10. A method of converting digital input signals bits into representative analog signals, comprising operations of:

providing a digital input signal to an accumulator that includes an input and a carry output;

responsive to receiving the digital input signal, the accumulator repeatedly performing operations comprising;

computing a current N-bit sum by adding the digital input signal with a last-computed version of the sum; and

providing a first prescribed signal on the carry output if the current sum cannot be expressed in N bits, otherwise providing a different prescribed signal on the carry output if the current sum can be expressed in N bits; and

applying an analog filter to signals on the carry output to generate an analog output signal representative of the value of the digital input signal.

11. The method of claim 10, the digital input signal comprising a signal of multiple binary bits in parallel.

12. The method of claim 10, the operations further comprising:

during the repeated operations of the accumulator, sequentially providing multiple further digital input signals to the accumulator.

13. The method of claim 10, where:

the operations further comprise;

operating the accumulator to provide a sum signal representing the current sum upon a sum output; and

storing the sum signal in a register; and

the operation of computing a current N-bit sum comprises operating the accumulator to add the digital input signal with the sum signal from the register.

14. The method of claim 10, the first prescribed signal being a binary one.

21. The method of claim 12, the first prescribed signal being a binary one.

15. A method of providing a serial binary output signal having pulses that are optimized as to their even distribution over time, comprising operations of:

receiving specification of time between adjacent pulses in a desired serial binary output;

computing a digital input value that will yield the specified time between pulses when provided as input to an accumulator configured to perform operations to continually update a current sum by adding the current input value, the operations comprising;

computing an N-bit current sum by adding a digital input signal with a last-computed version of the sum; and

providing a first prescribed signal on the carry output if the current sum cannot be expressed in N bits, otherwise providing a different prescribed signal on the carry output if the current sum can be expressed in N bits; and

providing the computed digital input value to the accumulator.

16. The method of claim 15, where the operation of receiving specification of time between pulses comprises receiving an specification of average time between pulses.

17. The method of claim 15, the operations further comprising:

receiving specification of a new time between pulses, and in response, repeating the computing and providing operations accordingly.

18. The method of claim 15, further comprising directing signals on the carry output to additional circuitry having a trigger line and being activated upon receipt of a trigger signal thereon.

19. The method of claim 18, the additional circuitry comprising a processor and the trigger line comprising a hardware interrupt line.

20. The method of claim 15, where:

the operations further comprise;

operating the accumulator to provide a sum signal representing the current sum upon a sum output; and

storing the sum signal in a register; and

the operation of computing a current sum comprises operating the accumulator to add the digital input signal with an output of the sum from the register.

22. A method of providing a serial binary output signal having pulses that are optimized as to their even distribution over time, comprising operations of:

receiving specification of time between adjacent pulses in a desired serial binary output;

computing a digital input value that will yield the specified time between pulses when provided as input to an accumulator configured to perform operations to continually update a current sum by adding the current input value, the operations comprising;

computing an N-bit current sum by adding a digital input signal with a last-computed version of the sum; and

providing a first prescribed signal on the carry output if the current sum cannot be expressed in N bits, otherwise providing a different prescribed signal on the carry output if the current sum can be expressed in N bits;

providing the computed digital input value to the accumulator; and

solving an equation T=(2^N/n)*t for ‘

n’

, where ‘

T’

represents the specified time between pulses, ‘

n’

represents digital input value being computed, and ‘

t’

represents time required for the accumulator to perform one computation of a current sum.

23. The method of claim 22, where the accumulator operates according to a clock signal having a prescribed cycle, and ‘

t’

represents a length of the clock cycle.

24. A digital-to-analog converter, comprising:

an input to receive a digital input signal representing a digital input value;

a carry output; and

an accumulator configured to perform operations to continually update a current N-bit sum by adding the input value thereto, the operations comprising;

receiving a digital input signal at the input;

responsive to receiving the input signal, repeatedly performing operations comprising;

updating the current sum by adding the digital input value thereto, and

providing a first prescribed signal on the carry output if the current sum cannot be expressed in N bits, otherwise providing a different prescribed signal on the carry output if the current sum can be expressed in N bits; and

an analog filter coupled to the carry out for producing an analog output signal representative of the value of the digital input signal.