Low cost ball grid array package

• US 6,282,100 B1
• Filed: 07/01/1999
• Issued: 08/28/2001
• Est. Priority Date: 07/01/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Degani, Yinon, Frye, Robert Charles, Dudderar, Thomas Dixon
• Primary Examiner(s): Gandhi, Jayprakash N.
• Assistant Examiner(s): FOSTER, DAVID A
• Application Number:
  US09/346,100
• Time in Patent Office: 789 Days
• Field of Search: 361/760, 361/765, 361/767, 361/768, 361/772, 361/783, 174/250, 174/255, 174/256, 174/260, 174/261, 174/262, 257/734, 257/736, 257/737, 257/738, 228/180.22, 228/180.5
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.

Claims

1. An IC package comprising:

a. a first printed wiring board (first PWB) having an upper surface and a lower surface, and an array of first PWB wire bonding pads on said upper surface,

b. a semiconductor intermediate interconnection substrate (IIS) comprising;

i. a semiconductor substrate having an upper surface, a lower planar surface, and a center region on said upper surface,

ii. an array of IIS interconnection sites in said center region of said upper surface,

iii. an array of IIS wire bonding pads surrounding said center region of said upper surface,

iv. metallization runners interconnecting said array of IIS interconnection sites to said array of IIS wire bonding pads,

c. means for die bonding said lower planar surface of said IIS to the upper surface of said first PWB,

d. a single silicon IC chip attached to said IIS and having an array of IC chip interconnection sites on a surface thereof, said array of IC chip interconnection sites bonded to said array of IIS interconnection sites, and

e. means for wire bonding said array of IIS wire bonding pads to said array of first PWB wire bonding pads.

2. The IC package of claim 1 wherein the said substrate is silicon.

3. The IC package of claim 2 wherein the surface of the IIS is bare except for said metallization runners, said array of IIS wire bonding pads, and said array of IIS interconnection sites.

4. The IC package of claim 1 further including a second printed wiring board (second PWB), an array of second PWB interconnection sites on said second PWB, an array of first PWB interconnection sites on the lower surface of said first PWB, and interconnecting means for interconnecting said array of second PWB interconnection sites with said array of first PWB interconnection sites.

5. The IC package of claim 4 wherein said interconnecting means comprises a ball grid array.

6. The IC package of claim 5 wherein the number of IC interconnection sites is greater than 400.

8. The IC package of claim 6 wherein the surface of the IIS is bare except for said metallization runners, said array of IIS wire bonding pads and said array of IIS interconnection sites.

9. The IC package of claim 6 wherein said array of IC chip interconnection sites is an area array.

7. An IC package comprising:

a. a first printed wiring board (first PWB) having an upper surface and a lower surface, and an array of first PWB wire bonding pads on said upper surface,

b. a silicon intermediate interconnection substrate (IIS) comprising;

i. a quadrangular silicon substrate having an upper surface, a lower planar surface, a center region, a perimeter P, and an area A,

ii. an array of IIS interconnection sites in said center region of said upper surface, said array of IIS interconnection sites having an equivalent perimeter pitch D₁,

iii. an array of IIS wire bonding pads around said perimeter P, said array of IIS wire bonding pads having a pitch D₂, where D₂ is at least 1.15 D₁,

iv. metallization runners interconnecting said array of IIS interconnection sites to said array of IIS wire bonding pads,

c. means for die bonding said lower planar surface of said IIS to the upper surface of said first PWB,

d. means for wire bonding said array of IIS wire bonding pads to said array of first PWB wire bonding pads,

e. a second printed wiring board (second PWB), an array of second PWB interconnection sites on said second PWB, an array of first PWB interconnection sites on the lower surface of said first PWB, interconnecting means for interconnecting said array of second PWB interconnection sites with said array of first PWB interconnection sites, and

f. a single silicon IC chip attached to said IIS and having an area A₂, where A₁ is at least twice A₂, said single silicon IC chip having an array of IC chip interconnection sites on a surface thereof, said array of IC chip interconnection sites bonded to said array of IIS interconnection sites.