Intializing memory cells within a dynamic memory array prior to performing internal memory operations

• US 6,282,135 B1
• Filed: 02/12/2000
• Issued: 08/28/2001
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/503,049
• Time in Patent Office: 563 Days
• Field of Search: 365/149, 365/202, 365/203, 365/204, 365/226, 365/191, 365/194, 365/207
• US Class Current: 365/203
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. During an internally-controlled power-up sequence, respective memory cells within an array block are initialized to a respective non-intermediate voltage before enabling, during an internal memory operation, bit line sense amplifiers associated with the array block. Internal memory operations may then be performed as a result of external memory cycle requests received by the integrated circuit. In an exemplary embodiment, as the memory cell plate is being established at its proper voltage, all memory cells are forced to a low voltage level by simultaneously driving every word line high and by forcing all bit lines to VSS using the bit line equilibration circuitry. The word lines are then brought back low, and the operating bit line equilibrate voltage is properly established. Then, the very first internal memory operation occurs only after the voltage of the bit lines and memory cell plate have been properly established, and after all memory cells have been initialized at one of the two valid states (in this example, at VSS). Consequently, the bit line sense amplifiers, during the first cycles after power-up, do not have to try to sense memory cells having an initialized voltage near the bit line equilibration voltage, thereby avoiding potential meta-stable operation of the bit line sense amplifiers.

Claims

1. In an integrated circuit having a dynamic memory array block, a method of operating the integrated circuit comprising:

initializing each respective memory cell within the array block to a respective non-intermediate voltage during an internally-controlled power-up sequence before enabling bit line sense amplifiers associated with the array block during an internal memory operation.

2. A method as in claim 1 wherein:

each respective non-intermediate voltage comprises a voltage substantially different from a bit line equilibration voltage of the array block during normal operation after completion of the internally-controlled power-up sequence.

3. A method as in claim 2 wherein:

each respective non-intermediate voltage comprises a voltage substantially equal to either a low restore voltage level or a high restore voltage level of the bit line sense amplifiers within the array block under normal operation.

4. A method as in claim 1 further comprising:

performing a plurality of internal memory operations as part of the internally-controlled power-up sequence to initialize node voltages within other internal circuits prior to performing internal memory operations in response to memory commands.

5. A method as in claim 1 wherein the initializing step comprises:

forcing each true and complement bit line within the array block to a respective voltage substantially equal to either a low restore voltage level or a high restore voltage level of the bit line sense amplifiers within the array block during normal operation after completion of the internally-controlled power-up sequence; and

forcing a word line within the array block to a suitable voltage to turn on the access transistor within each memory cell associated with the word line.

6. A method as in claim 5 further comprising:

forcing simultaneously a plurality of word lines within the array block to a suitable voltage to turn on the access transistor within each memory cell associated with any of the plurality of word lines.

7. A method as in claim 6 further comprising:

forcing simultaneously all of the word lines within the array block to a suitable voltage to turn on the access transistor within each memory cell within the array block.

8. A method as in claim 5 wherein the initializing step comprises:

forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level; and

forcing each word line within the array block to a voltage above the threshold voltage of the access transistor within each memory cell within the array block.

9. A method as in claim 8 wherein each word line within the array block is forced sequentially to a voltage above the threshold voltage of the access transistor within each memory cell associated therewith.

10. A method as in claim 8 wherein groups of word lines within the array block are forced sequentially to a voltage above the threshold voltage of the access transistor within each memory cell associated therewith.

11. A method as in claim 8 wherein each word line within the array block is forced simultaneously to a voltage above the threshold voltage of the access transistor within each memory cell within the array block.

12. A method as in claim 8 further comprising:

if each bit line is coupled to an associated bit line sense amplifier through a transistor gated by an array select signal, ensuring that any array select signal associated with the array block is held active so that each bit line is actively coupled to an associated internal bit line sense amplifier node.

13. A method as in claim 8 wherein the step of forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level comprises:

if each bit line is coupled to a shared bit line equilibrate node through a transistor gated by an equilibrate signal, ensuring that any such equilibrate signal associated with the array block is held active so that each bit line is actively coupled to the shared bit line equilibrate node; and

forcing the shared bit line equilibrate node to the restore low voltage level.

14. A method as in claim 8 wherein the step of forcing each word line within the array block to a voltage above the threshold voltage of the access transistor within each memory cell within the array block comprises:

providing to a final driver stage of word line decoders associated with the array block a word line enable node which, during normal operation, functions as a virtual ground node to which deselected word lines are coupled so that such deselected word line remains at ground potential; and

forcing the word line enable node to a voltage greater than the threshold voltage of the access transistor within each memory cell within the array block.

15. A method as in claim 1 further comprising:

after the initializing step, performing internal memory operations in response to memory commands.

16. An integrated circuit comprising:

a dynamic memory array block including a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of memory cells each coupled to an associated one of the word lines and coupled to either the true or complement bit line of an associated one of the complementary bit line pairs; and

means for initializing respective memory cells within the array block to a respective non-intermediate voltage during an internally-controlled power-up sequence before enabling bit line sense amplifiers associated with the array block during an internal memory operation.

17. An integrated circuit as in claim 16 wherein the means for initializing comprises:

means for forcing each true and complement bit line within the array block to a voltage substantially equal to either a low restore voltage level or a high restore voltage level of the bit line sense amplifiers within the array block; and

means for forcing a word line within the array block to a suitable voltage to turn on the access transistor within each memory cell associated with the word line.

18. An integrated circuit as in claim 16 wherein the means for initializing comprises:

means for forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level; and

means for forcing each word line within the array block to a voltage above the threshold voltage of the access transistor within each memory cell within the array block.

19. An integrated circuit as in claim 18 wherein the means for forcing each word line within the array block comprises:

means for forcing all the word lines simultaneously to a voltage above the threshold voltage of the access transistor within each memory cell within the array block.

20. An integrated circuit comprising:

a dynamic memory array block including a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of memory cells each having an access transistor coupled to an associated one of the word lines and coupled to either the true or complement bit line of an associated one of the complementary bit line pairs;

a power-up controller circuit for detecting an application of power to the integrated circuit and for controlling in response thereto an internal power-up sequence for initializing the memory cells within the array block;

a plurality of bit line circuits responsive to the power-up controller circuit, each for coupling a respective bit line to a respective non-intermediate voltage; and

a plurality of word line circuits responsive to the power-up controller circuit, each for coupling a respective word line within the array block to a suitable voltage to turn on the access transistor within each memory cell associated with the respective word line.

21. An integrated circuit as in claim 20 wherein:

the plurality of word line circuits are arranged to simultaneously couple, responsive to the power-up controller circuit, more than one of the plurality of word lines within the array block to a suitable voltage to turn on the access transistor within each memory cell associated therewith.

22. An integrated circuit as in claim 20 wherein:

the plurality of word line circuits are arranged to simultaneously couple, responsive to the power-up controller circuit, all of the word lines within the array block to a suitable voltage to turn on the access transistor within each memory cell within the array block.

23. An integrated circuit as in claim 20 wherein:

the plurality of bit line circuits are arranged to simultaneously couple, responsive to the power-up controller circuit, a respective true bit line within the array block to one of either a high restore voltage level or a low restore voltage level, and to couple a corresponding complement bit line to the other of either the high restore voltage level or the low restore voltage level.

24. An integrated circuit as in claim 20 wherein:

the plurality of bit line circuits are arranged to simultaneously couple, responsive to the power-up controller circuit, each true and complement bit line within the array block to one of either a high restore voltage level or a low restore voltage level.

25. An integrated circuit as in claim 24 wherein:

the plurality of bit line circuits are arranged to simultaneously couple, responsive to the power-up controller circuit, each true and complement bit line within the array block to the low restore voltage level; and

the plurality of word line circuits are arranged to simultaneously couple, responsive to the power-up controller circuit, each word line within the array block to a voltage above the threshold voltage of the access transistor within each memory cell within the array block.

26. An integrated circuit comprising:

a dynamic memory array block including a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of memory cells each having an access transistor coupled to an associated one of the word lines and coupled to either the true or complement bit line of an associated one of the complementary bit line pairs;

a power-up controller circuit for detecting an application of power to the integrated circuit and for controlling in response thereto an internal power-up sequence for initializing the memory cells within the array block;

a plurality of bit line circuits responsive to the power-up controller circuit, each for simultaneously coupling a respective bit line to a low restore voltage level; and

a plurality of word line circuits responsive to the power-up controller circuit, each for simultaneously coupling a respective word line within the array block to a voltage above the threshold voltage of the memory cell access transistors.

27. An integrated circuit as in claim 26 further comprising:

a plurality of isolation devices respectively coupling a respective complementary bit line pair to an associated bit line sense amplifier, each of the isolation devices being controlled by an array select signal;

an array select signal circuit arranged to ensure, responsive to the power-up controller circuit, that each such array select signal associated with the array block is driven to a voltage sufficient to turn on each isolation device.

28. An integrated circuit as in claim 26 wherein the each of the plurality of bit line circuits comprises:

an equilibration device coupling, when enabled by an equilibrate signal coupled to a control terminal thereof, the respective bit line to a shared bit line equilibrate node;

and wherein the integrated circuit further includes

an equilibration signal circuit arranged to ensure, responsive to the power-up controller circuit, that each such equilibration signal associated with the array block is driven during an initialization period to a voltage sufficient to turn on each equilibration device; and

a bit line equilibrate node circuit arranged to maintain, during normal operation, the bit line equilibration voltage on the shared bit line equilibrate node and to ensure that each such shared bit line equilibrate node associated with the array block is driven to the low restore voltage level during the initialization period.

29. An integrated circuit as in claim 26 wherein the each of the plurality of word line circuits comprises:

a final driver stage coupled to a word line enable node; and

wherein the integrated circuit further includes

a word line enable circuit arranged to drive the word line enable node, during normal operation, to a virtual ground potential and to drive the word line enable node to a voltage above the access transistor threshold voltage during an initialization period.

30. In an integrated circuit including a dynamic memory array block incorporating a memory array cell plate node which, during normal operation, is biased at an intermediate voltage generally mid-way between a restore low voltage level and a restore high voltage level normally written into memory cells of the array block, and which array block incorporates a plurality of complementary bit line pairs which, during normal operation, are equilibrated to an intermediate voltage also generally mid-way between the restore low voltage level and the restore high voltage level, a method of preventing meta-stable latching of bit line sense amplifiers associated with the array block after power is applied to the array, said method comprising:

preventing internal memory operations; and

then forcing the memory array cell plate node to a voltage substantially equal to its normal intermediate voltage;

forcing each memory cell within the array block, during a time period ending no earlier than the memory array cell plate node substantially arriving at its forced voltage, to a respective non-intermediate voltage substantially different than the normal bit line equilibration voltage; and

then

equilibrating the complementary bit line pairs to a voltage substantially equal to the normal bit line equilibration voltage; and

then

allowing the bit line sense amplifiers associated with the array block to be enabled during an internal memory operation.

31. A method as in claim 30 wherein the memory cell forcing step comprises:

forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level; and

forcing each word line within the array block to a voltage above the threshold voltage of the memory cell access transistors.

32. A method as in claim 31 wherein the word line forcing step comprises:

sequentially forcing each word line within the array block to a voltage above the threshold voltage of the memory cell access transistors.

33. A method as in claim 31 wherein the word line forcing step comprises:

sequentially forcing groups of word lines within the array block to a voltage above the threshold voltage of the memory cell access transistors.

34. A method as in claim 31 wherein the word line forcing step comprises:

simultaneously forcing each word line within the array block to a voltage above the threshold voltage of the memory cell access transistors.

35. A method as in claim 31 further comprising:

providing a plurality of transistors respectively coupling a respective bit line to a respective bit line sense amplifier, each such transistor controlled by an associated signal; and

forcing any such associated signal active so that each bit line is actively coupled to an associated internal bit line sense amplifier node.

36. A method as in claim 31 wherein the step of forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level comprises:

providing a plurality of equilibrate transistors respectively coupling a respective bit line to a shared bit line equilibrate node when enabled by an equilibrate signal;

forcing any such equilibrate signal associated with the array block active so that each bit line is actively coupled to the shared bit line equilibrate node; and

forcing the shared bit line equilibrate node to the restore low voltage level.

37. A method as in claim 31 wherein the step of forcing each word line within the array block to a voltage above the threshold voltage of the access transistor within each memory cell within the array block comprises:

providing to a final driver stage of word line decoders associated with the array block a word line enable node which, during normal operation, is driven to a ground potential and functions as a virtual ground node to which deselected word lines are coupled so that such deselected word line remains at ground potential; and

forcing the word line enable node to a voltage greater than the threshold voltage of the access transistor within each memory cell within the array block.

38. A method as in claim 30 wherein the memory cell forcing step comprises:

providing a plurality of equilibrate transistors respectively coupling a respective bit line to a shared bit line equilibrate node when enabled by an equilibrate signal;

forcing any such equilibrate signal associated with the array block active so that each bit line is actively coupled to the shared bit line equilibrate node;

forcing the shared bit line equilibrate node to the restore low voltage level, thereby forcing both the true and complement bit line of each complementary bit line pair within the array block to the restore low voltage level;

providing to a final driver stage of word line decoders associated with the array block a word line enable node which, during normal operation, is driven to a ground potential and functions as a virtual ground node to which deselected word lines are coupled so that such deselected word lines remain at ground potential; and

forcing the word line enable node to a voltage greater than the threshold voltage of the access transistor within each memory cell within the array block, thereby forcing each word line within the array block to a voltage above the threshold voltage of the memory cell access transistors.