Image acquisition system

• US 6,282,462 B1
• Filed: 06/27/1997
• Issued: 08/28/2001
• Est. Priority Date: 06/28/1996
• Status: Expired due to Term

• Current Assignee: Metrovideo Incorporated
• Original Assignee: Metrovideo Incorporated
• Inventors: Hopkins, T. Eric
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): Garland, Steven R.
• Application Number:
  US08/884,589
• Time in Patent Office: 1,523 Days
• Field of Search: 382/153, 358/444, 358/474, 348/314, 348/311, 348/317-324, 700/259
• US Class Current: 700/259
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06T 1/0007 Image acquisition
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

An image acquisition system for machine vision systems decouples image acquisition from the transmission of the image to a host processor by using a programmable imager controller to selectively disable and enable the transmission of data to the host and by using a system of buffers to temporarily store image data pending allocation of memory. This enables the image acquisition system to acquire images asynchronously and to change the exposure parameters on a frame-by-frame basis without the latency associated with the allocation of memory for storage of the acquired image. The system architecture of the invention further permits interruption and resumption of image acquisition with minimal likelihood of missing data. Data throughput is further enhanced by transmitting to the host only that data corresponding to the region of interest within the image and discarding the data from outside of the region of interest at the camera stage.

Claims

1. A system for transmitting an image to a machine vision system having a host processor that allocates memory for storage of said image, said system comprising:

image acquisition means for acquiring at least a portion of said image in response to a trigger signal,

memory means for storing data representative of said image,

image transfer means for transferring said image from said image acquisition means to said memory means, said image transfer means including buffer memory means for temporarily storing said at least a portion of said image pending allocation of memory space from said memory means by the host processor, said buffer memory means including a data FIFO register coupled to receive data representative of said image from said image acquisition means and to release data representative of said image to the host processor in response to a release signal, and

direct memory address data transfer means for transferring said image data accumulated in said data FIFO register directly memory allocated in a host computer system, whereby said data transfer substantially reduces the number of times said system interrupts the host processor

wherein said image acquisition means can operate substantially independently of the allocation of memory by the host processor.

2. A system according to claim 1, wherein said buffer memory means comprises a plurality of registers, said plurality of registers being coupled to receive data representative of said image from said image acquisition means in response to said trigger signal and to release data representative of said image to the host processor in response to a release signal.

3. A system according to claim 1, wherein said image acquisition means comprises

photo-sensitive means for acquiring said image in response to said trigger signal containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said trigger signal and for programmably altering during acquisition of said image said selected image acquisition parameters.

4. A system according to claim 3, wherein said programmable control means includes a programmable imager controller circuit operating at a driving frequency, said programmable imager controller circuit adapted to be programmed with said image acquisition parameters and having means for automatically changing said driving frequency during acquisition of said image.

5. A system according to claim 3, wherein said buffer memory means comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired image, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said vertical register.

6. A system according to claim 5, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, and wherein said means for transferring tranfers a portion of said optical energy corresponding to a portion of said region of interest from said vertical register into said horizontal register, further comprising

disabling means for disabling transfer of said optical energy from said horizontal register during said transfer of optical energy from said vertical register into said horizontal register,

whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said vertical register to said horizontal register without actively removing said stored energy from said horizontal register.

7. A system according to claim 6, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, and wherein said means for transferring tranfers a portion of said energy stored in said vertical register corresponding to a portion of said region of interest into said horizontal register, further comprising

enabling means for enabling transfer of said optical energy stored in said horizontal register therefrom, and

disabling means for disabling transfer of optical energy from said vertical register into said horizontal register during said transfer of optical energy out of said horizontal register.

8. A system according to claim 1, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without substantially interrupting the host processor.

9. A system according to claim 1, further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is at least substantially full, thereby permitting reliable transfer of data corresponding to said image.

10. A system according to claim 9, wherein said image is composed of a plurality of lines, and wherein said interrupt means is capable of interrupting said acquisition of said image between said lines corresponding to said image.

11. A system according to claim 1, further comprising feedback means coupled between said image acquisition means and said data FIFO register for monitoring said status of said register and for transferring an interrupt signal to said image acquisition means to interrupt said acquisition of said image, said feedback means including interrupt means coupled to said data FIFO register for generating said interrupt signal when said data FIFO register is at least substantially full, whereby said interrupt means immediately and temporarily interrupts said acquisition of said image.

12. A system according to claim 1, wherein said image acquired by said image acquisition means includes a plurality of pixels, further comprising pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means.

13. A system according to claim 12, wherein said pixel correction means comprises

second memory means for storing a plurality of predetermined pixel correction values corresponding to each pixel of said image, and

multiplier means for multiplying each pixel of said image by said corresponding pixel correction value, thereby forming a corrected pixel.

14. A system according to claim 12, wherein said pixel correction means is separate from the host processor and performs said pixel correction in real time.

15. A machine vision system for acquiring an image, said system comprising:

image acquisition means for acquiring said image, said image acquisition means including means for altering image acquisition parameters prior to acquisition of said image and image correction means for multiplying a subset of said image by a correction value corresponding to said subset of said image;

memory means for storing said image;

image transfer means for transferring said image from said programmable image

acquisition means to said memory means, said image transfer means including

means for interrupting transfer of said image at an interruption point, and

means for resuming transfer of said image from said interruption point.

whereby resuming said acquisition of said image at said interruption point substantially prevents loss of data corresponding to said image.

16. A system according to claim 15, wherein said image acquisition means includes means for defining at least one region of interest, said at least one region of interest being a subset of said image, and means for acquiring said at least one region of interest.

17. A system according to claim 15, wherein said image acquisition means comprises means for programmably controlling the amount of optical energy corresponding to said image collected by a camera.

18. A system according to claim 15, wherein said image acquisition means includes trigger means for initiating acquisition of said image in response to a trigger signal.

19. A system according to claim 15, wherein said image correction means comprises

image input means for accepting data representative of said image,

storage means for storing said correction factor corresponding to said subset of said image, said storage means having input means responsive to an external signal,

multiplier means coupled to said storage means and coupled to said image input means for multiplying said correction value with said corresponding subset of said image, and

data counter means coupled to said storage table means for determining correspondence between said subset of said image and said correction value.

20. A system according to claim 15, wherein said image acquisition means includes means for encoding an acquisition time into said image.

21. A system according to claim 20, wherein said means for encoding an acquisition time into said image comprises kernel level software in communication with a host processor, said kernel level software being responsive to a camera trigger signal.

22. A system according to claim 15, wherein said image transfer means includes a data FIFO memory for storing data and for releasing data asynchronously.

23. A system according to claim 15, wherein said image transfer means includes programmable imager data transfer means for selectively controlling the rate at which data travels from said image acquisition means to said memory means.

24. A system according to claim 23, wherein said programmable imager transfer means comprises

first data storage means for storing said image acquired by said image acquisition means,

second data storage means coupled to said first data storage means,

first shift means for shifting a subset of said image stored in said first data storage means to said second data storage means thereby storing said subset of said image in said second data storage means,

second shift means for shifting said subset of said image stored in said second data storage means to said memory means, and

disable means for disabling said second shift means during operation of said first shift means and to disable said first shift means during operation of said second shift means.

25. A system according to claim 15, wherein said image transfer means comprises

first data storage means for storing said image acquired by said image acquisition means,

second data storage means coupled to said first data storage means,

first shift means for shifting a subset of said image stored in said first data storage means to said second data storage means thereby storing said subset of said image in said second data storage means,

second shift means for shifting said subset of said image stored in said second data storage means to said memory means, and

disable means for disabling said second shift means during operation of said first shift means and to disable said first shift means during operation of said second shift means, said disable means including

means for operating said second shift means when said image stored in said second data storage means is inside said region of interest, and

second disabling means for disabling said second shift means and operating said first shift means when said image stored in said second data storage means is outside said region of interest.

26. A system according to claim 15, wherein said image acquisition means comprises

photo-sensitive means for acquiring said image in response to an acquisition signal containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said acquisition signal and for programmably altering during acquisition of said image said selected image acquisition parameters.

27. A system according to claim 26, wherein said programmable control means includes a programmable imager controller circuit operating at a driving frequency, said programmable imager controller circuit being adapted to be programmed with said image acquisition parameters and having means for automatically changing said driving frequency during acquisition of said image.

28. A system according to claim 26, wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal substantially independently of allocation of the memory by the host processor.

29. A system according to claim 26, wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal in parallel with and substantially independently of allocation of the memory by the host processor.

30. A system according to claim 15, wherein said memory means comprises a data FIFO register, wherein said means for transferring transfers said image into said register.

31. A system according to claim 30, further comprising data transfer means for transferring said image data accumulated in said data FIFO register to the host computing system.

32. A system according to claim 31, wherein said transfer of data from said data FIFO register is a direct memory address transfer, thereby substantially reducing the number of times the system interrupts the host processor.

33. A system according to claim 15, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without interrupting said host processor.

34. A system according to claim 15, wherein said means for interrupting is coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is full, thereby permitting reliable transfer of data corresponding to said image.

35. A system according to claim 15, wherein said means for transferring is adapted for immediately and temporarily interrupting said acquisition of said image.

36. An image acquisition system for connection to a machine vision system for acquiring an image of an object, said system having a host processor and comprising:

image acquisition means for acquiring said image of the object, said imaging including a plurality of pixels, said image acquisition means including

photo-sensitive means for acquiring said image in response to an acquisition signal containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said acquisition signal and for programmably altering during acquisition of said image said selected image acquisition parameters,

memory means for storing at least a portion of said image,

pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means, said pixel correction means including

second memory means for storing a plurality of pre-determined pixel correction values corresponding to each pixel of said image, and

multiplier means for multiplying each pixel of said image by said corresponding pixel correction value, thereby forming a corrected pixel, and

transfer means for transferring said image from said image acquisition means to said memory means.

37. The image acquisition system of claim 36, wherein said programmable control means includes a programmable imager controller circuit that operates at a driving frequency, said programmable imager controller circuit being adapted to be programmed with said image acquisition parameters including means for automatically changing said driving frequency during acquisition of said image.

38. The image acquisition system of claim 36, wherein said memory means comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired image, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said vertical register.

39. The image acquisition system of claim 38, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, further comprising

second means for transferring a portion of said optical energy corresponding to a portion of said region of interest from said vertical register to said horizontal register, and

disabling means for disabling transfer of optical energy from said horizontal energy during said transfer of optical energy from said vertical register into said horizontal register,

whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said vertical register to said horizontal register without actively removing said transferred energy from said horizontal register.

40. The image acquisition system of claim 39, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, further comprising

second means for transferring a portion of said energy stored in said vertical register corresponding to a portion of said region of interest to said horizontal register,

enabling means for enabling transfer of optical energy stored in said horizontal register therefrom, and

disabling means for disabling transfer of optical energy from said vertical register into said horizontal register during said transfer of optical energy out of said horizontal register.

41. The image acquisition system of claim 36, wherein said memory means comprises a data FIFO register, wherein said transfer means transfers said image into said register.

42. The image acquisition system of claim 41, further comprising second transfer means for transferring said image data accumulated in said data FIFO register to the host computing system.

43. The image acquisition system of claim 42, wherein said second transfer means transfers data from said data FIFO register substantially independently of a memory manager of the host computing system.

44. The image acquisition system of claim 41, further comprising memory address transfer means for transferring said data stored in said data FIFO register directly to an address in the host computing system, thereby substantially reducing the number of times the system interrupts the host processor.

45. The image acquisition system of claim 41, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without interrupting said host processor.

46. The image acquisition system of claim 41, further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is full, thereby permitting reliable transfer of data corresponding to said image.

47. The image acquisition system of claim 46, wherein said interrupt means is capable of interrupting said acquisition of said image between lines corresponding to said image.

48. The image acquisition system of claim 46, wherein said interrupt means is adapted for immediately and temporarily interrupting said acquisition of said image.

49. The image acquisition system of claim 36, wherein said pixel correction means is separate from one of the host processor and the host computing system and performs said pixel correction in real time.

50. A system for transmitting an image to a machine vision system having a host processor that allocates memory for storage of said image, said system comprising:

image acquisition means for acquiring at least a portion of said image in response to a trigger signal, said portion of said image including a plurality of pixels,

memory means for storing data representative of said image,

pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means, said pixel correction means including

second memory means for storing a plurality of pre-determined pixel correction values corresponding to each pixel of said image, and

multiplier means for multiplying each pixel of said image by said corresponding pixel correction value, thereby forming a corrected pixel, and

image transfer means for transferring said image from said image acquisition means to said memory means, said image transfer means including buffer memory means for temporarily storing said at least a portion of said image pending allocation of memory space from said memory means by the host processor,

wherein said image acquisition means can operate substantially independently of the allocation of memory by the host processor.

51. A system according to claim 50, wherein said buffer memory means comprises a data FIFO register, said data FIFO being coupled to receive data representative of said image from said image acquisition means and to release data representative of said image to the host processor in response to a release signal.

52. A system according to claim 51, further comprising direct memory address data transfer means for transferring said image data accumulated in said data FIFO register directly memory allocated in the host computing system, whereby said data transfer substantially reduces the number of times said system interrupts the host processor.

53. A system according to claim 51, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without substantially interrupting the host processor.

54. A system according to claim 51, further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is at least substantially fall, thereby permitting reliable transfer of data corresponding to said image.

55. A system according to claim 54, wherein said image is composed of a plurality of lines, and wherein said interrupt means is capable of interrupting said acquisition of said image between said lines corresponding to said image.

56. A system according to claim 51, further comprising feedback means coupled between said image acquisition means and said data FIFO register for monitoring said status of said register and for transferring an interrupt signal to said image acquisition means to interrupt said acquisition of said image, said feedback means including interrupt means coupled to said data FIFO register for generating said interrupt signal when said data FIFO register is at least substantially full, whereby said interrupt means immediately and temporarily interrupts said acquisition of said image.

57. A system according to claim 50, wherein said buffer memory means comprises a plurality of registers, said plurality of registers being coupled to receive data representative of said image from said image acquisition means in response to said trigger signal and to release data representative of said image to the host processor in response to a release signal.

58. A system according to claim 50, wherein said image acquisition means comprises

photo-sensitive means for acquiring said image in response to said trigger signal containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said trigger signal and for programmably altering during acquisition of said image said selected image acquisition parameters.

59. A system according to claim 58, wherein said programmable control means includes a programmable imager controller circuit operating at a driving frequency, said programmable imager controller circuit adapted to be programmed with said image acquisition parameters and having means for automatically changing said driving frequency during acquisition of said image.

60. A system according to claim 58, wherein said buffer memory means comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired image, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said vertical register.

61. A system according to claim 60, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, and wherein said means for transferring transfers a portion of said optical energy corresponding to a portion of said region of interest from said vertical register into said horizontal register, further comprising

disabling means for disabling transfer of said optical energy from said horizontal register during said transfer of optical energy from said vertical register into said horizontal register,

whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said vertical register to said horizontal register without actively removing said stored energy from said horizontal register.

62. A system according to claim 61, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, and wherein said means for transferring transfers a portion of said energy stored in said vertical register corresponding to a portion of said region of interest into said horizontal register, further comprising

enabling means for enabling transfer of said optical energy stored in said horizontal register therefrom, and

disabling means for disabling transfer of optical energy from said vertical register into said horizontal register during said transfer of optical energy out of said horizontal register.

63. A system according to claim 58, wherein said pixel correction means is separate from the host processor and performs said pixel correction in real time.

64. A machine vision system for acquiring an image, said system comprising:

programmable image acquisition means for acquiring said image, said programmable image acquisition means including means for altering image acquisition parameters prior to acquisition of said image;

memory means for storing said image, said memory means including

a data FIFO register for accumulating image data from said programmable image acquisition means, and

data transfer means for transferring said image data from said data FIFO register to a host computing system by a direct memory address transfer, thereby substantially reducing the number of times the system interrupts the host processor;

image transfer means for transferring said image from said programmable image acquisition means to said memory means, said image transfer means including

means for interrupting transfer of said image at an interruption point, and

means for resuming transfer of said image from said interruption point

whereby resuming said acquisition of said image at said interruption point substantially prevents loss of data corresponding to said image.

65. A system according to claim 64, wherein said image acquisition means includes means for defining at least one region of interest, said at least one region of interest being a subset of said image, and means for acquiring said at least one region of interest.

66. A system according to claim 64, wherein said image acquisition means comprises means for programmably controlling the amount of optical energy corresponding to said image collected by a camera.

67. A system according to claim 64, wherein said image acquisition means includes trigger means for initiating acquisition of said image in response to a trigger signal.

68. A system according to claim 64, wherein said image acquisition means includes image correction means for multiplying a subset of said image by a correction value corresponding to said subset of said image.

69. A system according to claim 68, wherein said image correction means comprises

image input means for accepting data representative of said image

storage means for storing said correction factor corresponding to said subset of said image, said storage means having input means responsive to an external signal,

multiplier means coupled to said storage means and coupled to said image input means for multiplying said correction value with said corresponding subset of said image, and

data counter means coupled to said storage table means for determining correspondence between said subset of said image and said correction value.

70. A system according to claim 64, wherein said image acquisition means includes means for encoding an acquisition time into said image.

71. A system according to claim 70, wherein said means for encoding an acquisition time into said image comprises kernel level software in communication with a host processor, said kernel level software being responsive to a camera trigger signal.

72. A system according to claim 64, wherein said image transfer means includes a data FIFO memory for storing data and for releasing data asynchronously.

73. A system according to claim 64, wherein said image transfer means includes programmable imager data transfer means for selectively controlling the rate at which data travels from said image acquisition means to said memory means.

74. A system according to claim 73, wherein said programmable imager transfer means comprises

first data storage means for storing said image acquired by said image acquisition means,

second data storage means coupled to said first data storage means,

first shift means for shifting a subset of said image stored in said first data storage means to said second data storage means thereby storing said subset of said image in said second data storage means,

second shift means for shifting said subset of said image stored in said second data storage means to said memory means, and

disable means for disabling said second shift means during operation of said first shift means and to disable said first shift means during operation of said second shift means.

75. A system according to claim 64, wherein said image transfer means comprises

first data storage means for storing said image acquired by said image acquisition means,

second data storage means coupled to said first data storage means,

first shift means for shifting a subset of said image stored in said first data storage means to said second data storage means thereby storing said subset of said image in said second data storage means,

second shift means for shifting said subset of said image stored in said second data storage means to said memory means, and

disable means for disabling said second shift means during operation of said first shift means and to disable said first shift means during operation of said second shift means, said disable means including

means for operating said second shift means when said image stored in said second data storage means is inside said region of interest, and

second disabling means for disabling said second shift means and operating said first shift means when said image stored in said second data storage means is outside said region of interest.

76. A system according to claim 64, wherein said image acquisition means comprises

photo-sensitive means for acquiring said image in response to an acquisition signal containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said acquisition signal and for programmably altering during acquisition of said image said selected image acquisition parameters.

77. A system according to claim 76, wherein said programmable control means includes a programmable imager controller circuit operating at a driving frequency, said programmable imager controller circuit being adapted to be programmed with said image acquisition parameters and having means for automatically changing said driving frequency during acquisition of said image.

78. A system according to claim 77, further comprising data transfer means for transferring said image data accumulated in said data FIFO register to the host computing system.

79. A system according to claim 77, wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal in parallel with and substantially independently of allocation of the memory by the host processor.

80. A system according to claim 76, wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal substantially independently of allocation of the memory by the host processor.

81. A system according to claim 64, wherein said memory means comprises a data FIFO register, wherein said means for transferring transfers said image into said register.

82. A system according to claim 81, wherein said transfer of data from said data FIFO register is a direct memory address transfer, thereby substantially reducing the number of times the system interrupts the host processor.

83. A system according to claim 64, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without interrupting said host processor.

84. A system according to claim 64, wherein said means for interrupting is coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is full, thereby permitting reliable transfer of data corresponding to said image.

85. A system according to claim 64, wherein said means for transferring is adapted for immediately and temporarily interrupting said acquisition of said image.

86. An image acquisition system for connection to a machine vision system for acquiring an image of an object, said system having a host processor and comprising:

image acquisition means for acquiring said image of the object, said image acquisition means including

photo-sensitive means for acquiring said image in response to an acquisition signal containing selected image acquisition parameters, and

programmable control means in circuit with said photo-sensitive means for generating said acquisition signal and for programmably altering during acquisition of said image said selected image acquisition parameters,

memory means for storing at least a portion of said image, said memory means including

a data FIFO register for accepting an image from said image acquisition means, and

memory address transfer means for transferring said image stored in said data FIFO register directly to an address in the host processor, thereby substantially reducing the number of times the system interrupts the host processor, and

transfer means for transferring said image from said image acquisition means to said memory means.

87. The image acquisition system of claim 86, wherein said programmable control means includes a programmable imager controller circuit operating at a driving frequency, said programmable imager controller circuit being adapted to be programmed with said image acquisition parameters and having means for automatically changing said driving frequency during acquisition of said image.

88. The image acquisition system of claim 86, wherein said memory means comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired image, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said vertical register.

89. The image acquisition system of claim 88, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, further comprising

second means for transferring a portion of said optical energy corresponding to a portion of said region of interest from said vertical register to said horizontal register, and

disabling means for disabling transfer of optical energy from said horizontal energy during said transfer of optical energy from said vertical register into said horizontal register,

whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said vertical register to said horizontal register without actively removing said transferred energy from said horizontal register.

90. The image acquisition system of claim 89, wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, further comprising

second means for transferring a portion of said energy stored in said vertical register corresponding to a portion of said region of interest to said horizontal register,

enabling means for enabling transfer of optical energy stored in said horizontal register therefrom, and

disabling means for disabling transfer of optical energy from said vertical register into said horizontal register during said transfer of optical energy out of said horizontal register.

91. The image acquisition system of claim 86, further comprising second transfer means for transferring said image data accumulated in said data FIFO register to the host processor.

92. The image acquisition system of claim 86, further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without interrupting said host processor.

93. The image acquisition system of claim 86, further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is full, thereby permitting reliable transfer of data corresponding to said image.

94. The image acquisition system of claim 93, wherein said interrupt means includes means for interrupting said acquisition of said image between lines corresponding to said image.

95. The image acquisition system of claim 93, wherein said interrupt means includes means for immediately and temporarily interrupting said acquisition of said image.

96. The image acquisition system of claim 86, wherein said image acquired by said image acquisition means includes a plurality of pixels, further comprising pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means.

97. The image acquisition system of claim 96, wherein said pixel correction means comprises

second memory means for storing a plurality of pre-determined pixel correction values corresponding to each pixel of said image, and

multiplier means for multiplying each pixel of said image by said corresponding pixel correction value, thereby forming a corrected pixel.

98. The image acquisition system of claim 96, wherein said pixel correction means is separate from the host processor and performs said pixel correction in real time.