Integrated processor and programmable data path chip for reconfigurable computing

• US 6,282,627 B1
• Filed: 05/25/2000
• Issued: 08/28/2001
• Est. Priority Date: 06/29/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chameleon Systems, Inc.
• Inventors: Phillips, Christopher E., Cooke, Laurence H., Wong, Dale
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/446,762
• Time in Patent Office: 460 Days
• Field of Search: 712/37, 712/11, 712/13, 712/15, 712/20
• US Class Current: 712/15
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable “hard-wired” functions.

Claims

1. An integrated circuit, comprising:

fine-grain reconfigurable control logic having bit level oriented cells;

coarse-grain reconfigurable datapath logic having multiple bit datapath cells; and

memory means coupled to the reconfigurable control logic and the reconfigurable datapath logic for defining multiple configurations of the reconfigurable control logic and the reconfigurable datapath logic.

2. The apparatus of claim 1, further comprising reconfigurable memory, wherein said memory means is coupled to the reconfigurable memory for defining multiple configurations of the reconfigurable memory.

3. The apparatus of claim 2, further comprising a microprocessor coupled to at least one of said reconfigurable control logic, said reconfigurable datapath logic, and said reconfigurable memory.

4. The apparatus of claim 3, wherein the microprocessor is coupled to multiple ones of said reconfigurable control logic, said reconfigurable datapath logic, and said reconfigurable memory.

5. The apparatus of any of the preceding claims, wherein said memory means comprises multiple logical memory planes.

6. The apparatus of claim 5, further comprising means for performing hardware-controlled transfer of data between logical memory planes.

7. The apparatus of claim 6, wherein said transfer of data is direct plane-to-plane transfer.

8. The apparatus of claim 7, wherein the direct plane-to-plane transfer is completed within a single cycle of the microprocessor.

9. The apparatus of claim 1, wherein said memory means comprises means for simultaneously addressing multiple memory locations located in different memory rows and different memory columns to write identical data into the multiple memory locations, whereby an amount of data needed to completely configure at least one of said reconfigurable control logic and said reconfigurable datapath logic is substantially reduced.

10. The apparatus of claim 9, wherein at least one of the reconfigurable control logic and the reconfigurable datapath logic comprises multiple cells, each cell requiring a predetermined number of bits of configuration information to configure the cell, wherein at least a portion of said memory means is organized into data words having a word length equal to the predetermined number of bits.

11. The apparatus of claim 3, further comprising a bus coupled to the microprocessor and, coupled to the bus, at least one of a bus controller for controlling an external bus and a memory controller for controlling an external memory.

12. A reconfigurable computing method using an adaptive compute engine including a microprocessor, a memory, and an array of reconfigurable logic elements having fine-grain reconfigurable control logic and coarse-grain reconfigurable datapath logic, the method comprising the steps of:

executing instructions on the microprocessor;

in response to one or more instructions, loading multiple sets of configuration data into the memory;

passing data to the coarse-grain reconfigurable datapath logic; and

passing control information to the fine-grain reconfigurable datapath logic.

13. The method of claim 12, wherein the multiple sets of configuration data comprises at least one set of effective configuration data applied to the reconfigurable logic elements and at least one set of other configuration data not applied to the reconfigurable logic elements, the method comprising the further step of, in response to a predetermined instruction, physically swapping the effective configuration data and the other configuration data.

14. The method of claim 12, comprising the further step of, in response to one or more instructions, passing data and control information between the microprocessor and the array of reconfigurable logic elements.

15. The apparatus of claim 14, comprising the further steps of, in response to one or more instructions:

performing at least one of loading a set of configuration data from external memory to become the effective configuration data and physically swapping a set of configuration data to cause it to become the effective configuration data; and

causing the array of reconfigurable logic element to perform data processing in accordance with the effective configuration data.

16. An integrated circuit, comprising:

fine-grain reconfigurable control logic;

coarse-grain reconfigurable datapath logic; and

memory means coupled to the reconfigurable control logic and the reconfigurable datapath logic for defining multiple configurations of the reconfigurable control logic and the reconfigurable datapath logic;

wherein said memory means comprises means for simultaneously addressing multiple memory locations located in different memory rows and different memory columns to write identical data into the multiple memory locations, whereby an amount of data needed to completely configure at least one of said reconfigurable control logic and said reconfigurable datapath logic is substantially reduced.

17. The apparatus of claim 16, further comprising reconfigurable memory, wherein said memory means is coupled to the reconfigurable memory for defining multiple configurations of the reconfigurable memory.

18. The apparatus of claim 17, further comprising s a microprocessor coupled to at least one of said reconfigurable control logic, said reconfigurable datapath logic, and said reconfigurable memory.

19. The apparatus of claim 18, wherein the microprocessor is coupled to multiple ones of said reconfigurable control logic, said reconfigurable datapath logic, and said reconfigurable datapath logic.

20. The apparatus of claim 16, wherein said memory means comprises multiple logical memory planes.

21. The apparatus of claim 20, further comprising means for performing hardware-controlled transfer of data between logical memory planes.

22. The apparatus of claim 21, wherein said transfer of data is direct plane-to-plane transfer.

23. The apparatus of claim 22 wherein the direct plane-to-plane transfer is completed within a single cycle of the microprocessor.

24. The apparatus of claim 16, wherein at least one of the reconfigurable control logic and the reconfigurable datapath logic comprises multiple cells, each cell requiring a predetermined number of bits of configuration information to configure the cell, wherein at least a portion of said memory means is organized into data words having a word length equal to the predetermined number of bits.

25. The apparatus of claim 18, further comprising a bus coupled to the microprocessor and, coupled to the bus, at least one controller for controlling an external bus and a memory controller for controlling an external memory.

26. A reconfigurable computing method using an adaptive compute engine including a microprocessor, a memory, and an array of reconfigurable logic elements, the method comprising the steps of:

executing instructions on the microprocessor;

loading multiple sets of configuration data into memory in response to one or more instructions; and

simultaneously addressing multiple memory locations located in different memory rows and different memory columns to write identical data into the multiple memory locations, whereby an amount of data needed to completely configure the logic elements is substantially reduced.

27. The method of claim 26, wherein the multiple sets of configuration data comprises at least one set of effective configuration data applied to the reconfigurable logic elements and at least one set of other configuration data not applied to the reconfigurable logic elements, the method comprising the further step of, in response to a predetermined instruction, physically swapping the effective configuration data and the other configuration data.

28. The method of claim 26 comprising the further step of, in response to one or more instructions, passing data and control information between the microprocessor and the array of reconfigurable logic elements.

29. The method of claim 28, comprising the further steps of, in response to one or more instructions:

performing at least one of loading a set of configuration data from external memory to become the effective configuration data and physically swapping a set of configuration data to cause it to become the effective configuration data; and

causing the array of reconfigurable logic element to perform data processing in accordance with the effective configuration data.