Method of manufacture of a stacked electrostatic ink jet printer

• US 6,284,147 B1
• Filed: 07/10/1998
• Issued: 09/04/2001
• Est. Priority Date: 07/15/1997
• Status: Expired due to Fees

• Current Assignee: Zamtec Limited (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia
• Primary Examiner(s): Gulakowski, Randy
• Assistant Examiner(s): Ahmed, Shamim
• Application Number:
  US09/112,827
• Time in Patent Office: 1,152 Days
• Field of Search: 216/27, 347/55, 438/21
• US Class Current: 216/27
• CPC Class Codes: B41J 2/14314 Structure of ink jet print heads with electrostatically actuated membrane
• CPC Class Codes: B41J 2/14427 Structure of ink jet print heads with thermal bend detached actuators
• CPC Class Codes: B41J 2/1623 bonding and adhesion
• CPC Class Codes: B41J 2/1628 dry etching
• CPC Class Codes: B41J 2/1629 wet etching
• CPC Class Codes: B41J 2/1631 photolithography
• CPC Class Codes: B41J 2/1632 machining
• CPC Class Codes: B41J 2/1635 dividing the wafer into individual chips
• CPC Class Codes: B41J 2/1639 sacrificial molding
• CPC Class Codes: B41J 2/1642 thin film formation by CVD [chemical vapor deposition]
• CPC Class Codes: B41J 2/1643 thin film formation by plating
• CPC Class Codes: B41J 2/1645 thin film formation by spincoating
• CPC Class Codes: B41J 2/1646 thin film formation by sputtering
• CPC Class Codes: B41J 2/1648 Production of print heads with thermal bend detached actuators
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: B41J 2002/041 Electromagnetic transducer
• CPC Class Codes: B41J 2002/14346 Ejection by pressure produced by thermal deformation of ink chamber, e.g. buckling
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G06K 1/121 by printing code marks applying code marks to labels B65C9/46; marking or coding completed packages B65B61/26
• CPC Class Codes: G06K 19/06037 : multi-dimensional coding
• CPC Class Codes: G06K 7/14 : using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence
• CPC Class Codes: G06K 7/1417 : 2D bar codes
• CPC Class Codes: G11C 11/56 : using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: H04N 23/00 : Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 : Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

This patent describes a method of manufacturing a stacked electrostatic ink jet print head wherein an array of nozzles are formed on a substrate utilizing planar monolithic deposition, lithographic and etching processes. Multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilizing standard VLSI/ULSI processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate plane.

Claims

1. A method of manufacture of an ink jet print head arrangement including a series of nozzle chambers, said method comprising the steps of:

(a) utilising an initial semiconductor wafer having an electrical circuitry layer thereon including etched vias for interconnection of said circuitry with subsequent layers;

(b) repeatedly depositing a series of planar layers on said electrical circuitry layer, said planar layers including a first conductive layer, a second conductive layer and an intermediate compressible non conductive layer;

(c) etching said planar layers so as to form a series of stacked alternating structures;

(d) isolating at least one first edge of said stacked alternating structure;

(e) etching said second conductive layer and said intermediate compressible layer along said edge so as to expose said first conductive layer;

(f) isolating a second edge of said stacked alternating structure;

(g) etching said first conductive layer and said intermediate compressible layer along said second edge so as to expose said second conductive layer;

(h) depositing and etching a third conductive layer having first portions interconnected along said first edge with said first conductive layer and a second portion interconnected along said second edge with said second conductive layer, said first and second portions being interconnected with corresponding portions in said electrical circuitry layer;

(i) depositing and etching a sacrificial material layer on said wafer, said etching forming a mould for a subsequent nozzle chamber layer;

(j) depositing and etching an insert material layer over said sacrificial layer so as to form a nozzle chamber surrounding said conductive layers in addition to an ink ejection hole;

(k) etching an ink supply channel through portions of said wafer to interconnect with said nozzle chamber; and

(l) etching away said sacrificial material layer.

2. A method as claimed in claim 1 wherein said step (j) includes etching a series of small holes in a wall of said nozzle chamber interconnecting said chamber with the ambient atmosphere.

3. A method as claimed in claim 1 wherein said first conductive layer and second conductive layer are formed from different conductive materials.

4. A method as claimed in claim 1 wherein said compressible layer comprises substantially elastomer.

5. A method as claimed in claim 4 wherein said method further includes foaming the elastomer along said edges.

6. A method as claimed in claim 1 wherein said ink supply channel is etched through said wafer from a back surface of said wafer.

7. A method as claimed in claim 1 further including the step of depositing corrosion barriers over portions of said arrangement so as to reduce corrosion effects.

8. A method as claimed in claim 1 wherein the etching of layers includes etching vias so as to allow for the electrical interconnection with portions of subsequent layers.

9. A method as claimed in claim 1 wherein said wafer comprises a double side polished CMOS wafer.

10. A method as claimed in claim 1 wherein at least said step (l) is also utilised to simultaneously separate said wafer into separate print heads.