Process to reduce post cycling program VT dispersion for NAND flash memory devices

• US 6,284,602 B1
• Filed: 09/20/1999
• Issued: 09/04/2001
• Est. Priority Date: 09/20/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chang, Kent K., Huang, Allen U., He, Yue-Song
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/399,526
• Time in Patent Office: 715 Days
• Field of Search: 438/258, 438/261, 438/264, 438/266, 438/267, 438/981
• US Class Current: 438/258
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

In one embodiment, the present invention relates to a method of forming a NAND type flash memory device involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N₂O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

Claims

1. A method of forming a NAND type flash memory device, comprising:

growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area;

removing a portion of the first oxide layer in the flash memory cell area of the substrate;

growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area;

annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N₂O and NO for a period of time from about 1 minute to about 15 minutes;

depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å

to about 1,000 Å

;

depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer;

depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and

forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

2. The method of claim 1, wherein the first oxide layer has a thickness from about 130 Å

to about 170 Å

.

3. The method of claim 1, wherein the second oxide layer in the flash memory cell area has a thickness from about 50 Å

to about 110 Å

.

4. The method of claim 1, wherein the first and second oxide layers in the select gate area have a combined thickness from about 140 Å

to about 200 Å

.

5. The method of claim 1, wherein the annealing is conducted at a temperature from about 800°

C. to about 1,200°

C.

6. The method of claim 1, wherein the annealing is conducted under an atmosphere comprising from about 60% to about 99% of the inert gas and from about 1% to about 40% of at least one of N₂O and NO.

7. The method of claim 1, wherein the annealing is conducted at a temperature from about 900°

C. to about 1,100°

C. for a period of time from about 2 minutes to about 10 minutes.

8. The method of claim 1, wherein the first and second oxide layers in the select gate area and the second oxide layer in the flash memory cell area have a thickness after annealing that is from about 0.5% to about 15% in size greater than the thickness prior to annealing.

9. A method of forming a NAND type flash memory device, comprising:

forming a first oxide layer over at least a portion of a substrate, the substrate including a core region with a flash memory cell area and a select gate area, and a periphery region with a high voltage transistor area and a low voltage transistor area;

forming a nitride layer over at least a portion of the first oxide layer;

removing the nitride layer and the first oxide layer from the core region of the substrate exposing the substrate in the core region;

forming a second oxide layer over at least a portion of the core region of the substrate;

removing a portion of the second oxide layer in the flash memory cell area of the core region of the substrate;

forming a third oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the second oxide layer in the select gate area;

annealing the second oxide layer and the third oxide layer in the select gate area of the core region of the substrate and the third oxide layer in the flash memory cell area of the core region of the substrate in an atmosphere comprising an inert gas and at least one of N₂O and NO;

depositing a first in situ doped amorphous silicon layer over at least a portion of the substrate;

depositing a dielectric layer over at least a portion of the substrate;

removing the dielectric layer, the first in situ doped amorphous silicon layer, the nitride layer, and the first oxide layer in the periphery region of the substrate;

forming a high voltage transistor gate oxide in the high voltage transistor area of the periphery region of the substrate and low voltage transistor gate oxide in the low voltage transistor area of the periphery region of the substrate;

depositing a second doped amorphous silicon layer over at least a portion of the substrate; and

forming a flash memory cell in the flash memory cell area of the core region of the substrate, a select gate transistor in the select gate area of the core region of the substrate, a high voltage transistor in the high voltage transistor area of the periphery region of the substrate, and a low voltage transistor in the low voltage transistor area of the periphery region of the substrate.

10. The method of claim 9, wherein the nitride layer has a thickness from about 100 Å

to about 400 Å and

first oxide layer has a thickness from about 100 Å

to about 400 Å

.

11. The method of claim 9, wherein the nitride layer has a thickness from about 200 Å

to about 300 Å and

first oxide layer has a thickness from about 200 Å

to about 300 Å

.

12. The method of claim 9, wherein the annealing is conducted at a temperature from about 800°

C. to about 1,200°

C. for a period of time from about 1 minute to about 15 minutes.

13. The method of claim 9, wherein the annealing is conducted at a temperature from about 900°

C. to about 1,100°

C. for a period of time from about 2 minutes to about 10 minutes.

14. The method of claim 9, wherein the dielectric layer has a thickness from about 110 Å

to about 150 Å and

comprises a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.

15. The method of claim 9, wherein after annealing the second oxide layer and the third oxide layer in the select gate area have a thickness from about 140 Å

to about 200 Å and

the third oxide layer in the flash memory cell area has a thickness from about 50 Å

to about 110 Å

.