Method for fabricating semiconductor power integrated circuit

• US 6,284,605 B1
• Filed: 10/28/1999
• Issued: 09/04/2001
• Est. Priority Date: 10/28/1998
• Status: Expired due to Term

• Current Assignee: Uniloc 2017 LLC (SoftBank Group Corp.)
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Dae-Yong, Koo, Jin-gun, Kim, Sang-Gi, Kim, Jong-Dae
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/428,403
• Time in Patent Office: 677 Days
• Field of Search: 438/138, 438/268, 438/197, 438/212, 438/216-224, 438/135, 438/424, 438/435, 438/287
• US Class Current: 438/268
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Claims

1. A method for fabricating a semiconductor power integrated circuit, comprising the steps of:

a) forming a semiconductor structure having at least one active region, wherein an active region includes a first well region for forming a channel and a source region and a drift region for forming a drain region;

b) forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure;

c) forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor structure;

d) forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer; and

e) performing a selective tapered etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a trench isolation layer pattern, a gate oxide layer pattern.

2. The method as recited in claim 1, wherein the step c) includes the step of performing a thermal treatment process to the first TEOS-oxide layer.

3. The method as recited in claim 2, wherein the field oxide layer pattern, the gate oxide layer pattern and a trench isolation layer pattern have tapered side walls by performing a wet etching through a buffered oxide etchant.

4. The method as recited in claim 3, wherein the thermal treatment process is performed at a temperature of about 850°

C. for 30 minutes.

5. The method as recited in claim 4, wherein the step b) includes the step of forming a thermal oxide layer on an entire structure after forming the trench.

6. The method as recited in claim 5, wherein first TEOS-oxide layer is formed to a thickness of 8000 Å

to 15000 Å

, and the second TEOS-oxide layer is formed to a thickness of 2000 Å

to 5000 Å

.

7. The method as recited in claim 6, wherein a thickness of the thermal oxide layer is of about 500 Å

.

8. The method as recited in claim 6, wherein the step c) includes the steps of:

forming a Spin On Glass (SOG) layer on the first TEOS-oxide layer; and

planarizing the first TEOS-oxide layer by performing an etch back to the SOG layer and a part of the first TEOS-oxide layer.

9. The method as recited in claim 4, wherein the etching process of the step b) is performed using a mixed gas of HBr and SiF₄, the mixed gas containing 45 percent He and O₂.

10. The method as recited in claim 1, wherein the step a) includes the steps of:

forming a buried insulating layer on a semiconductor substrate of a first conductivity type; and

forming an epitaxial layer of a second type conductivity type on the buried insulating layer.

11. The method as recited in claim 10, wherein the step e) includes the steps of:

forming a channel and a source region of the second conductivity type on the first well region of the first conductivity type and a drift region and a drain region of the second conductivity type by selectively implanting ions of impurity;

forming a source region of the first conductivity type on the first region of the first conductivity type by selectively implanting ions of impurity; and

forming a gate electrode on the gate oxide layer pattern.

12. The method as recited in claim 11, wherein the step c) includes the step of performing a thermal treatment process to the first TEOS-oxide layer.

13. The method as recited in claim 12, wherein the field oxide layer pattern, the trench isolation layer pattern, the gate oxide layer pattern, and the diode insulating layer pattern have tapered side walls by performing a wet etching through a buffered oxide etchant.

14. The method as recited in claim 12, wherein the thermal treatment process is performed at a temperature of about 850°

C. for 30 minutes.

15. The method as recited in claim 14, wherein the step b) includes the step of forming a thermal oxide layer on an entire structure after forming the trench.

16. The method as recited in claim 15, wherein the first TEOS-oxide layer is formed to a thickness of 8000 Å

to 15000 Å

, and the second TEOS-oxide layer is formed to a thickness of 2000 Å

to 5000 Å

.

17. The method as recited in claim 16, wherein a thickness of the thermal oxide layer is of about 500 Å

.

18. The method as recited in claim 17, wherein the step c) includes the steps of:

forming a Spin On Glass (SOG) layer on the first TEOS-oxide layer; and

planarizing the first TEOS-oxide layer by performing an etch back to the SOG layer and a part of the first TEOS-oxide layer.

19. The method as recited in claim 18, wherein the etching process of the step b) is performing using a mixed gas of HBr and SiF₄, the mixed gas containing 45 percent He and O₂.