Semiconductor device combining a MOSFET structure and a vertical-channel trench-substrate field effect device

• US 6,285,057 B1
• Filed: 11/17/1999
• Issued: 09/04/2001
• Est. Priority Date: 11/17/1999
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Hopper, Peter J., Pichler, Christoph
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/441,497
• Time in Patent Office: 657 Days
• Field of Search: 257/330, 257/332
• US Class Current: 257/330
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A semiconductor device that provides for substrate current exiting a MOSFET structure, and hence the performance thereof, to be independently and controllably tuned. The semiconductor device includes a semiconductor substrate of a first conductivity type, a conventional MOSFET structure disposed thereon, and at least one vertical-channel trench-substrate field effect device disposed in the semiconductor substrate. The vertical-channel trench-substrate field effect device includes a vertical-channel region beneath the MOSFET structure. During operation, substrate current exiting the MOSFET structure can be independently and controllably tuned by applying a potential bias to the vertical-channel trench-substrate field effect device that “pinches-off” the vertical-channel region. The vertical-channel trench-substrate field effect device includes an expanded trench that extends from an upper surface of the semiconductor substrate to beneath the MOSFET structure and a dielectric shallow trench spacer (e.g., silicon dioxide or silicon nitride dielectric shallow trench spacer) that is disposed along an upper portion of the sidewall of the expanded trench. The vertical-channel trench-substrate field effect device also includes a SiO₂ trench liner layer disposed on those portions of the sidewall of the expanded trench that are not covered by the dielectric shallow trench spacer, and an electrically conductive trench fill layer (e.g., in-situ doped polysilicon) in the expanded trench. The vertical-channel region can be “pinched-off,” and the substrate current exiting the MOSFET structure independently and controllably tuned, by applying a potential bias to the electrically conductive trench fill layer. Also, a process for manufacturing the semiconductor device that is compatible with conventional IC manufacturing techniques.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

an MOSFET device structure formed in the semiconductor substrate; and

at least one vertical-channel trench-substrate field effect device formed in the semiconductor substrate, the vertical-channel trench-substrate field effect device including a vertical-channel region formed vertically beneath the MOSFET structure.

2. The semiconductor device of claim 1, wherein the MOSFET structure includes:

a gate silicon dioxide layer on the semiconductor substrate;

a silicon gate layer overlying the gate silicon dioxide layer; and

source and drain regions of a second conductivity type formed in the semiconductor substrate;

wherein the at least one vertical-channel trench-substrate field effect device includes;

an expanded trench extending from the upper surface of the semiconductor substrate to beneath the MOSFET structure;

a dielectric shallow trench spacer disposed along the sidewall of an upper portion of the expanded trench and adjacent to the source and drain regions of the MOSFET structure;

a SiO₂ trench liner layer disposed on the sidewalls of the expanded trench; and

an electrically conductive trench fill layer formed in the expanded trench.

3. The semiconductor device of claim 1 wherein, during operation of the semiconductor device, the application of a potential bias to the electrically conductive trench fill layer controllably tunes substrate current exiting the MOSFET device structure through the vertical-channel region.

4. The semiconductor device of claim 2 wherein the vertical-channel trench-substrate field effect device further includes an electrical contact to the electrically conductive trench fill layer, and wherein, during operation of the semiconductor device, the application of a potential bias to the electrically conductive trench fill layer via the electrical contact controllably tunes substrate current exiting the MOSFET device structure through the vertical-channel region.

5. The semiconductor device of claim 2 wherein the electrically conductive trench fill layer is an in-situ doped polysilicon layer.

6. The semiconductor device of claim 2 wherein the narrowest width of the vertical-channel region is in the range of 0.08 to 0.12 microns.

7. The semiconductor device of claim 1 wherein the MOSFET device structure is a portion of an ESD protection device.

8. The semiconductor device of claim 1 wherein the MOSFET device structure is a portion of a CMOS device structure.