Adjustable high-trigger-voltage electrostatic discharge protection device

• US 6,285,062 B1
• Filed: 05/12/1999
• Issued: 09/04/2001
• Est. Priority Date: 05/12/1999
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Ken W.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US09/310,288
• Time in Patent Office: 846 Days
• Field of Search: 257/173, 257/174, 257/356, 257/357, 257/358, 257/359, 257/360, 257/361, 257/362, 257/363
• US Class Current: 257/361
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

An apparatus includes a first doped region, a first doped well, a first doped plug, a second doped plug, and an isolation structure. The first doped well is disposed within the first doped region. The first doped plug is disposed within the first doped well. The second doped plug is disposed within the first doped region. The isolation structure is disposed between the first and second doped plugs. A method includes providing a first doped region. A first doped well is formed within the first doped region, and a first doped plug is formed within the first doped well. A second doped plug is formed within the first doped region, and an isolation structure is formed between the first and second doped plugs.

Claims

1. An apparatus, comprising:

a first doped region;

a first doped well disposed within the first doped region;

a first doped plug disposed at a location within the first doped well, said location selected to provide a first breakover voltage between the first doped plug and the first doped region;

a second doped plug disposed within the first doped region; and

an isolation structure disposed between the first and second doped plugs,

wherein a second breakover voltage exists between the first doped well and the first doped region, and the first breakover voltage is less than the second breakover voltage.

2. The apparatus of claim 1, further comprising a second doped well disposed within the first doped region, wherein the second doped plug is disposed within the second doped well.

3. The apparatus of claim 1, wherein the first doped plug has a first boundary, the first doped well has a second boundary, and the first breakover voltage is dependent on the proximity of the first boundary to the second boundary.

4. The apparatus of claim 2, wherein the second doped well has a first boundary, the second doped plug has a second boundary, and the second boundary is proximate the first boundary.

5. The apparatus of claim 1, wherein the isolation structure is at least one of a LOCOS oxide and a surface trench filled with an oxide.

6. The apparatus of claim 1, wherein the isolation structure is a gate terminal comprising a dielectric layer disposed adjacent to at least a portion of the first doped region and a conductor layer disposed above at least a portion of the dielectric layer.

7. The apparatus of claim 1, further comprising a conductor layer disposed above at least a portion of the first and second doped plugs.

8. The apparatus of claim 1, wherein the first doped region comprises a p-type material.

9. The apparatus of claim 1, wherein the first and second doped plugs comprise an n-type material.

10. The apparatus of claim 2, wherein the first and second doped wells comprise an n-type material, and the doping concentrations of the first and second doped wells are less than the doping concentrations of the first and second doped plugs.

11. The apparatus of claim 1, wherein the first breakover voltage is within a range of about 10-50V.

12. An apparatus, comprising:

a p-type semiconductor substrate;

a first n-well disposed within the semiconductor substrate;

a first n-plug disposed at a location within the first n-well, said location selected to provide a first breakover voltage between the first doped plug and the first doped region;

a second n-plug disposed within the p-type semiconductor substrate;

an isolation structure disposed between the first and second n-plugs,

wherein a second breakover voltage exists between the first n-well and the p-type semiconductor substrate, and the first breakover voltage is less than the second breakover voltage.

13. The apparatus of claim 12, further comprising a second n-well disposed within the p-type semiconductor substrate, wherein the second n-plug is disposed within the second n-well.

14. The apparatus of claim 13, wherein the second n-well has a first boundary, the second n-plug has a second boundary, and the second boundary is proximate the first boundary.

15. The apparatus of claim 12, wherein the first n-plug has a first boundary, the first n-well has a second boundary, and the first breakover voltage is dependent on the proximity of the first boundary to the second boundary.

16. The apparatus of claim 12, wherein the isolation structure is at least one of a LOCOS oxide and a surface trench filled with an oxide.

17. The apparatus of claim 12, wherein the isolation structure is a gate terminal comprising a dielectric layer disposed adjacent to at least a portion of the first doped region and a conductor layer disposed above at least a portion of the dielectric layer.

18. The apparatus of claim 12, wherein the first breakover voltage is within a range of about 10-50V.

19. An integrated circuit, comprising:

an external bond pad;

a voltage source;

an ESD protection device coupled between the external bond pad and the voltage source,

wherein the ESD protection device comprises;

a first doped region;

a first doped well disposed within the first doped region;

a first doped plug disposed at a location within the first doped well and coupled to the external bond pad, said location selected to provide a first breakover voltage between the first doped plug and the first doped region;

a second doped plug disposed within the first doped region and coupled to the voltage source; and

an isolation structure disposed between the first and second doped plugs,

wherein the ESD protection device comprises a second breakover voltage between the first doped well and the first doped region, and the first breakover voltage is less than the second breakover voltage, and

at least one integrated component coupled to the ESD protection device.

20. The integrated circuit of claim 19, wherein the ESD protection device further comprises a second doped well disposed within the first doped region, wherein the second doped plug is disposed within the second doped well.

21. The integrated circuit of claim 19, wherein the first doped plug of the ESD protection device has a first boundary, the first doped well has a second boundary, and the first breakover voltage is dependent on the proximity of the first boundary to the second boundary.

22. The integrated circuit of claim 20, wherein the second doped well of the ESD protection device has a first boundary, the second doped plug has a second boundary, and the second boundary is proximate the first boundary.

23. The integrated circuit of claim 19, wherein the isolation structure of the ESD protection device is at least one of a LOCOS oxide and a surface trench filled with an oxide.

24. The integrated circuit of claim 19, wherein the first doped region of the ESD protection device comprises a p-type material.

25. The integrated circuit of claim 19, wherein the first and second doped plugs of the ESD protection device comprise an n-type material.

26. The integrated circuit of claim 19, wherein the first and second doped wells of the ESD protection device comprise an n-type material, and the doping concentrations of the first and second doped wells are less than the doping concentrations of the first and second doped plugs.

27. The integrated circuit of claim 19, wherein the second breakover voltage of the ESD protection device is within a range of about 10-50V.

28. The integrated circuit of claim 19, wherein the voltage source is coupled to ground.

29. The integrated circuit of claim 19, wherein the voltage source is coupled to a power supply.

30. The integrated circuit of claim 19, further comprising a buffer coupled between the ESD protection device and the integrated components.

31. The integrated circuit of claim 19, wherein the integrated component is an anti-fuse network.