I/O buffer circuit with pin multiplexing

• US 6,285,211 B1
• Filed: 12/13/1999
• Issued: 09/04/2001
• Est. Priority Date: 07/16/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Inventors: Patel, Rakesh H., Butts, Michael R., Sample, Stephen P., Norman, Kevin A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): PAIK, STEVEN SANGYUL
• Application Number:
  US09/460,535
• Time in Patent Office: 631 Days
• Field of Search: 326/37, 326/38, 326/39, 326/40, 326/41, 326/93
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

Claims

1. An integrated circuit comprising:

a field programmable gate array (FPGA) core;

an input/output buffer circuit;

an input/output pin coupled to the input/output buffer circuit;

an output multiplexer capable of receiving “

N”

signals and time-multiplexing the “

N”

signals onto the input/output pin;

an input multiplexer capable of receiving a time-multiplexed signal and de-multiplexing the time-multiplexed signal into “

N”

separate signals; and

“

N”

bi-directional core connections between the FPGA core and the input/output buffer circuit for either transmitting signals from the FPGA core to the input/output buffer circuit or for transmitting signals from the input/output buffer to the FPGA core; and

wherein “

N”

is any integer greater than 1.

2. A circuit for implementing re-configurable logic, comprising:

a core;

a connection to the core capable of transmitting a signal bi-directionally;

an input/output pin capable of transmitting a signal bi-directionally;

an input/output (I/O) buffer configured to receive a first signal from the connection and a second signal from the input/output pin, and to output the first signal to the input/output pin and the second signal to the connection in a time-multiplexed manner.

3. An integrated device for implementing re-configurable logic, comprising:

a core;

a first input/output buffer coupled to the core via a first connection and a second connection, the first and second connections capable of transmitting signals bi-directionally between the core and the first input/output buffer, the first input/output buffer capable of receiving a first signal from the core via the first connection and a second signal from the core via the second connection, and configured to time-multiplex the first and second signals onto an input/output pin.

4. The integrated device of 3 wherein the first input/output buffer is configured to transmit the first signal from the first connection to the input/output pin along a first path, and to transmit the second signal from the second connection to the input/output pin along a second path, wherein the first and second paths are substantially independent of each other.

5. The integrated device of 3 wherein the first input/output buffer is capable of receiving a third signal and a fourth signal via the input/output pin in a time-multiplexed manner, transmitting the third signal to the core via the first connection, and transmitting the fourth signal to the core via the second connection.

6. The integrated device of 5 wherein the first input/output buffer is configured to transmit the third signal to the first connection along a third path, and to transmit the fourth signal to the second connection along a fourth path, wherein the third and fourth paths are substantially independent of each other.

7. The integrated device of 5 wherein the first input/output buffer is capable of transmitting the third and fourth signals to the core after a programmable delay.

8. The integrated device of 5 wherein the first input/output buffer further comprises:

a receiver configured to receive the third signal and the fourth signal;

a first input multiplexer configured to receive the first signal from the first connection and the third signal from the receiver; and

a second input multiplexer configured to receive the second signal from the second connection and the fourth signal from the receiver.

9. The integrated device of 8 wherein the first input/output buffer further comprises:

a first flip-flop configured to receive the first signal and the second signal from the first input multiplexer;

a second flip-flop configured to receive the third signal and the fourth signal from the second input multiplexer; and

an output multiplexer configured to receive the first signal from the first flip-flop and the third signal from the second flip-flop.

10. The integrated device of 3 further comprising:

a second input/output buffer coupled to the core via a third connection; and

wherein the first input/output buffer is coupled to the third connection whereby the first input/output buffer may utilize the third connection when it is not being used by the second input/output buffer.

11. The integrated device of 10 wherein a signal received from the core via the third connection is used to control a mode of operation of the first input/output buffer.

12. The integrated device of 3 wherein the first input/output buffer is capable of time-multiplexing the first and second signals asynchronously relative to tirnings of the first and second signals.

13. A circuit for implementing reconfigurable logic, comprising:

a first circuit comprising;

a first core; and

a first input/output buffer coupled to the first core via a first connection and a second connection, the first and second connections capable of transmitting signals bi-directionally between the first core and the first input/output buffer, the first input/output buffer capable of receiving a first signal from the first core via the first connection and a second signal from the first core via the second connection, and configured to time-multiplex the first and second signals onto an input/output pin; and

a second circuit comprising;

a second core; and

a second input/output buffer coupled to the second core via a third connection and a fourth connection, the third and fourth connections capable of transmitting signals bi-directionally between the second core and the second input/output buffer, the second input/output buffer capable of receiving the first signal and the second signal from the input/output pin in a time-multiplexed manner, transmitting the first signal to the second core via the third connection, and transmitting the second signal to the second core via the fourth connection.

14. The circuit of claim 13 further comprising a clock that causes the first input/output buffer and the second input/output buffer to operate in a time-multiplexed manner.

15. The circuit of claim 13 wherein the input/output pin is capable of capable of transmitting signals bi-rectionally between the first input/output buffer and the second input/output buffer.

16. In an integrated circuit device comprising a core, an input/output buffer, and an input/output pin, a method of communicating signals between the core and the input/output pin, the method comprising:

coupling the input/output buffer to the core via a first connection capable of transmitting a signal bi-directionally;

receiving, at the input/output buffer, a first signal from the core via the first connection;

receiving, at the input/output buffer, a second signal via the input/output pin; and

outputting the first signal to the input/output pin and the second signal to the first connection in a time-multiplexed manner.

17. In an integrated circuit device comprising a core, an input/output buffer, and an input/output pin, a method of communicating signals between the core and the input/output pin, the method comprising:

coupling the first input/output buffer to the core via a first connection and a second connection, the first and second connections capable of transmitting signals bi-directionally between the core and the first input/output buffer;

receiving, at the first input/output buffer, a first signal from the core via the first connection;

receiving, at the first input/output buffer, a second signal from the core via the second connection; and

time-multiplexing the first and second signals onto the input/output pin.

18. The method of claim 17 further comprising:

receiving, at the first input/output buffer, a third signal and a fourth signal via the input/output pin in a time-multiplexed manner,

transmitting the third signal to the core via the first connection; and

transmitting the fourth signal to the core via the second connection.

19. The method of claim 17 further comprising:

coupling a second input/output buffer to the core via a third connection; and

controlling a mode of operation of the first input/output buffer based on a signal received from the core via the third connection.