Delay locked loop circuits and methods of operation thereof

• US 6,285,225 B1
• Filed: 07/23/1999
• Issued: 09/04/2001
• Est. Priority Date: 08/08/1998
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Chu, Yong-gyu, Lee, Jae-hyeong
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/361,022
• Time in Patent Office: 774 Days
• Field of Search: 327/544, 327/158, 327/149, 327/236, 327/237, 327/270, 327/3
• US Class Current: 327/158
• CPC Class Codes: H03K 2005/00045 Dc voltage control of a capacitor or of the coupling of a capacitor as a load
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

A delay locked loop circuit includes a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit. A delay control circuit is responsive to the input clock signal and to the delayed clock signal, and applies a delay control signal to the variable delay circuit based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal. In an embodiment, the delay control circuit includes a phase comparator circuit that receives the input clock signal and the delayed clock signal and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the reference clock signal leads or lags the second edge of the input clock signal. A delay control signal generating circuit applies a delay control signal to the variable delay circuit responsive to the phase comparison signal. Related operating methods also are provided.

Claims

1. A delay locked loop circuit, comprising:

a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit; and

a delay control circuit, responsive to the input clock signal and to the delayed clock signal, that generates the delay control signal and applies the delay control signal to the variable delay circuit based on a comparison of a transition of the delayed clock signal corresponding to a first transition of the input clock signal to a second transition of the input clock signal that follows the first transition of the input clock signal.

2. A circuit according to claim 1, wherein said delay control circuit generates the delay control signal based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal;

wherein the edge of the delayed clock signal is the transition of the delayed clock signal, the first edge of the input clock signal is the first transition of the input clock signal, and the second edge of the input clock signal is the second transition of the input clock signal.

3. A circuit according to claim 2, wherein said delay control circuit comprises:

a phase comparator circuit that receives the input clock signal and the delayed clock signal and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the input clock signal leads or lags the second edge of the input clock signal; and

a delay control signal generating circuit that applies the delay control signal to said variable delay circuit responsive to the phase comparison signal.

4. A circuit according to claim 3, wherein said delay control signal generating circuit comprises a charge pump that generates the delay control signal responsive to the phase comparison signal.

5. A circuit according to claim 3:

wherein said phase comparator circuit asserts a first phase comparison signal responsive to the edge of the delayed clock signal corresponding to the first edge of the input clock signal lagging the second edge of the input clock signal and asserts a second phase comparison signal responsive to the edge of the delayed clock signal corresponding to the first edge of the input clock signal leading the second edge of the input clock signal; and

wherein said delay control signal generating circuit generates the delay control signal responsive to the first and second phase comparison signals.

6. A circuit according to claim 5, wherein said delay control signal generating circuit comprises a charge pump that generates the delay control signal responsive to the first and second phase comparison signals.

7. A circuit according to claim 6:

wherein said variable delay circuit receives the delay control signal at a delay control signal input thereof;

wherein said charge pump comprises;

a capacitor coupled to said delay control signal input of said variable delay circuit;

a current source;

a current sink;

a first switch operative to couple said current source to said capacitor when a first one of the first and second phase comparison signals is asserted;

and

a second switch operative to couple said current sink to said capacitor when a second one of the first and second phase comparison signals is asserted.

8. A circuit according to claim 5, wherein said phase comparator circuit asserts the second phase comparison signal for a time extending from the edge of the delayed clock signal corresponding to the first edge of the input clock signal to the second edge of the input clock signal if the edge of the delayed clock signal corresponding to the first edge of the input clock signal leads the second edge of the input clock signal, and wherein said phase comparator circuit asserts the first phase comparison signal for a time extending from the second edge of the input clock signal to the edge of the delayed clock signal corresponding to the first edge of the input clock signal if the edge of the delayed clock signal corresponding to the first edge of the input clock signal lags the second edge of the input clock signal.

9. A circuit according to claim 8, wherein said phase comparator circuit comprises:

a first flip-flop having a data input, a clock input, a reset input and an output, said first flip-flop receiving the input clock signal at the clock input and a first data signal at the data input, clocking the first data signal to produce a second data signal at the output responsive to an edge of the input clock signal and resetting the second data signal responsive to an initialization signal at the reset input;

a second flip-flop having a clock input, a data input, a reset input and an output, said second flip-flop receiving the delayed clock signal at the clock input, the first data signal at the input and clocking the first data signal to produce the second phase comparison signal at the output of the second flip-flop responsive to an edge of the delayed clock signal and resetting the second phase comparison signal responsive to a reset signal at the reset input;

a third flip-flop having a clock input, a data input connected to the output of the first flip-flop, a reset input, and an output, said third flip-flop clocking the second data signal to produce the first phase comparison signal at the output of the third flip-flop responsive to an edge of the input clock signal and resetting the first phase comparison signal responsive to a reset signal at the reset input; and

a reset circuit coupled to the outputs of the second and third flip-flops and operative to apply a reset signal to the reset inputs of the second and third flip flops responsive to at least one of the first and second phase comparison signals or the initialization signal.

10. A circuit according to claim 1, wherein said variable delay circuit comprises:

a series-coupled plurality of inverters;

a plurality of capacitors, each having a first node coupled to a signal ground; and

a plurality of switches, a respective one of which is operative to variably couple a second node of a corresponding respective one of said plurality of capacitors to an output of a corresponding respective one of said plurality of inverters responsive to the delay control signal.

11. A method of producing a synchonized delayed signal from a periodic input signal, the method comprising the steps of:

generating a delayed signal from the periodic input signal using a delay circuit;

comparing a transition of the delayed signal corresponding to a first transition of the periodic input signal with a second transition of the periodic input signal that follows the first transition of the periodic input signal; and

varying the delay introduced by the delay circuit based on the comparison of the transition of the delayed signal corresponding to the first transition of the periodic input signal with the second transition of the periodic input signal.

12. A method according to claim 11, wherein the periodic input signal comprises an input clock signal, wherein the delayed signal comprises a delayed clock signal, and wherein the transitions of the periodic input signal and the delayed signals comprise edges.

13. A method according to claim 12, wherein said step of varying comprises at least one of the steps of:

asserting a first phase comparison signal responsive to an edge of the delayed clock signal corresponding to a first edge of the input clock signal lagging a second edge of the input clock signal that follows the first edge of the input clock signal;

or

asserting a second phase comparison signal responsive to the edge of the delayed clock signal corresponding to the first edge of the input clock signal leading the second edge of the input clock signal; and

wherein said step of varying further comprises the steps of;

generating a delay control signal responsive to the first and second phase comparison signals; and

varying the delay of the delayed clock signal responsive to the delay control signal.

14. A method according to claim 13, wherein said first step of varying comprises at least one of the steps of:

asserting the second phase comparison signal for a time extending from the edge of the delayed clock signal corresponding to the first edge of the input clock signal to the second edge of the input clock signal responsive to the edge of the delayed clock corresponding to the first edge of the input clock signal leading the second edge of the input clock signal;

or

asserting the first phase comparison signal for a time extending from the second edge of the input clock signal to the edge of the delayed clock signal corresponding to the first edge of the input clock signal responsive to the edge of the delayed clock signal corresponding to the first edge of the input clock signal lagging the second edge of the input clock signal.

15. A delay locked loop circuit, comprising:

a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit; and

a delay control circuit directly coupled to the variable delay circuit, responsive to the input clock signal and to the delayed clock signal, that generates the delay control signal and applies the delay control signal to the variable delay circuit based on a comparison of a transition of the delayed clock signal corresponding to a first transition of the input clock signal to a second transition of the input clock signal that immediately follows the first transition of the input clock signal.

16. A circuit according to claim 15:

wherein said delay control circuit generates the delay control signal based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal;

wherein the edge of the delayed clock signal is the transition of the delayed clock signal, the first edge of the input clock signal is the first transition of the input clock signal, and the second edge of the input clock signal is the second transition of the input clock signal.

17. A circuit according to claim 16, wherein said delay control circuit comprises:

a phase comparator circuit that receives the input clock signal and the delayed clock signal and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the input clock signal leads or lags the second edge of the input clock signal; and

a delay control signal generating circuit that applies the delay control signal to said variable delay circuit responsive to the phase comparison signal.

18. A delay locked loop circuit, comprising:

a variable delay circuit that receives an input clock signal and produces a delayed clock signal at an output thereof that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit; and

a delay control circuit, directly coupled to the output of the variable delay circuit and responsive to the input clock signal and to the delayed clock signal, that generates the delay control signal and applies the delay control signal to the variable delay circuit based on a comparison of a transition of the delayed clock signal corresponding to a first transition of the input clock signal to a second transition of the input clock signal that follows the first transition of the input clock signal.

19. A circuit according to claim 18:

wherein said delay control circuit generates the delay control signal based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal;

wherein the edge of the delayed clock signal is the transition of the delayed clock signal, the first edge of the input clock signal is the first transition of the input clock signal, and the second edge of the input clock signal is the second transition of the input clock signal.

20. A circuit according to claim 19, wherein said delay control circuit comprises:

a phase comparator circuit that receives the input clock signal and the delayed clock signal and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the input clock signal leads or lags the second edge of the input clock signal; and

a delay control signal generating circuit that applies the delay control signal to said variable delay circuit responsive to the phase comparison signal.