Feed-forward biasing for RF amplifiers

• US 6,285,239 B1
• Filed: 07/03/2000
• Issued: 09/04/2001
• Est. Priority Date: 03/29/1999
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Iyer, Nathan R., Kay, Michael R
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/609,510
• Time in Patent Office: 428 Days
• Field of Search: 330/133, 330/134, 330/136, 330/285, 327/530, 327/306, 327/531
• US Class Current: 327/531
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A

Abstract

Bias circuitry is configured to adjust bias current to one or more power amplifier stages based upon the level of the RF signal to be amplified. A feed-forward circuit senses the input power level of the signal to be amplified and dynamically adjusts the bias current for one or more amplifiers in the amplification path to ensure each amplifier is operating in a linear region for the given signal level. For amplifier configurations having multiple amplification stages, the bias circuitry provides proportional bias currents to each stage as necessary for the progressively increasing signal levels being amplified. The bias circuitry eliminates excessive quiescent bias currents that prior biasing techniques required to ensure linear operation by automatically increasing bias currents only as needed based on the effective magnitude of the RF signal to be amplified.

Claims

1. A biasing circuit for use with a radio frequency power amplifier, said biasing circuit comprising:

an input for receiving a radio frequency signal to be amplified by the radio frequency power amplifier;

a first transistor circuit coupled to said input and adapted to provide a bias control current having a value proportional to a relative magnitude of the radio frequency signal to be amplified; and

a second transistor circuit coupled to said first transistor circuit and adapted to output a bias current for the radio frequency power amplifier proportional to said bias control current based on mirroring said bias control current with a desired current gain;

wherein the magnitude of the radio frequency signal to be amplified by the radio frequency power amplifier is used to provide a proportional bias to the radio frequency power amplifier sufficient to insure substantially linear operation of the radio frequency power amplifier over varying levels of the radio frequency signal to be amplified.

2. The biasing circuit of claim 1 further comprising one or more additional transistor circuits coupled to said first transistor circuit, each adapted to output an additional bias current for use with one or more additional radio frequency power amplifiers successively arranged in an amplification signal path subsequent to the radio frequency power amplifier receiving the radio frequency signal to be amplified, wherein respective ones of said additional transistor circuits are matched to respective ones of the one or more additional radio frequency power amplifiers and configured with increasing current gains such that each successive radio frequency power amplifier in the amplification signal path receives a bias current proportionately larger than an immediately preceding radio frequency power in the amplification signal path.

3. The biasing circuit of claim 1 wherein said first transistor circuit is implemented using one or more bipolar junction transistors and said second transistor circuit is implemented using one or more field effect transistors.

4. The biasing circuit of claim 3 wherein said first and second transistor circuits are implemented in an integrated circuit device employing BiCMOS technology.

5. The biasing circuit of claim 1 wherein said biasing circuit is included in an integrated circuit device.

6. The biasing circuit of claim 5 wherein said integrated device includes the radio frequency power amplifier.

7. The biasing circuit of claim 6 wherein the radio frequency power amplifier is implemented using hetero-junction bipolar transistors.

8. An integrated circuit device adapted to provide bias currents to one or more radio frequency power amplifiers in an amplification signal path, said integrated circuit device comprising:

an input for receiving a radio frequency signal to be amplified by the one or more radio frequency power amplifiers;

a level sensing circuit coupled to said input and adapted to provide a bias control signal proportional to a relative magnitude of the radio frequency signal to be amplified; and

a biasing circuit coupled to said level sensing circuit and adapted to output bias currents to the one or more radio frequency power amplifiers, each said bias current proportional to said bias control signal, and said biasing circuit configured to scale said bias currents such that each successive radio frequency power amplifier in the amplification signal path receives a proportionately larger bias current.

9. The integrated circuit device of claim 8 further comprising a filter network disposed between said input and said level sensing circuit and adapted to provide said level sensing circuit with a filtered portion of the radio frequency signal to be amplified as received through said input.

10. The integrated circuit device of claim 8 wherein said level sensing circuit is a bipolar junction transistor circuit.

11. The integrated circuit device of claim 8 wherein said biasing circuit is a field effect transistor circuit.

12. The integrated circuit device of claim 8 further comprising the one or more radio frequency power amplifiers in the amplification signal path.

13. A biasing circuit for use with a radio frequency power amplifier, said biasing circuit comprising:

an input for receiving a radio frequency signal to be amplified by the radio frequency power amplifier;

level sensing circuitry comprising a filter circuit coupled to said input and a first transistor circuit coupled to said filter circuit and adapted to provide a bias control signal having a value proportional to a relative magnitude of the radio frequency signal to be amplified; and

biasing circuitry comprising a second transistor circuit coupled to said first transistor circuit and adapted to output a bias current to the radio frequency power amplifier that is proportional to said bias control signal;

wherein said level sensing circuitry substantially rectifies a radio frequency signal to be amplified by the radio frequency power amplifier to generate a substantially DC bias control signal that is proportional to a relative magnitude of the radio frequency signal to be amplified, such that said bias current output by said biasing circuitry is a DC bias current signal having a magnitude proportional to the relative magnitude of the radio frequency signal to be amplified.

14. The biasing circuit of claim 13 wherein said biasing circuitry further comprises one or more additional transistor circuits coupled to said first transistor circuit, each said additional transistor circuit adapted to output a bias current proportional to said bias control signal to additional radio frequency power amplifiers, wherein the additional radio frequency power amplifiers are successively arranged in an amplification signal path after the radio frequency amplifier receiving the radio frequency signal to be amplified.

15. The biasing circuit of claim 14 wherein said additional transistor circuits correspond to respective ones of the additional radio frequency power amplifiers, and further wherein each one of said additional transistor circuits is configured with a current gain based on a position in the amplification signal path of the respective additional radio frequency power amplifier.

16. The biasing circuit of claim 13 wherein said level sensing circuitry primarily comprises a bipolar junction transistor and said biasing circuitry primarily comprises a field effect transistor.

17. The biasing circuit of claim 13 wherein said bias control signal is an analog current signal, and further wherein said biasing circuitry mirrors said bias control signal with a desired current gain to produce said bias current.

18. A biasing circuit for use with multiple radio frequency power amplifier stages successively arranged in an amplification signal path, said biasing circuit comprising:

an input for receiving a portion of a radio frequency signal to be amplified by the multiple radio frequency power amplifiers in the amplification signal path;

a filter circuit coupled to said input and adapted to pass a desired range of signal frequencies within the radio frequency signal to be amplified;

a first transistor circuit coupled to said filter circuit and adapted to output a bias control current based on receiving a filtered portion of the radio frequency signal to be amplified through said filter circuit; and

a biasing transistor network coupled to said first transistor circuit and adapted to output multiple bias currents for biasing the multiple radio frequency power amplifiers based on mirroring said bias control current with a different current gain for each one of said multiple bias currents;

wherein the current gain for a given one of said multiple bias currents is configured based on a maximum signal amplitude expected for a corresponding one of the multiple radio frequency power amplifier stages, such that each successive radio frequency power amplifier stage receives a proportionately larger bias current from said biasing circuit.

19. The biasing circuit of claim 18 wherein said biasing circuit comprises a portion of an integrated circuit device.

20. The biasing circuit of claim 18 wherein said first transistor circuit primarily comprises a bipolar junction transistor arranged such that a base current is received into a base of said bipolar junction transistor through said filter circuit, and wherein said bipolar junction transistor is biased such that a collector current into a collector of said bipolar junction transistor is proportional to said base current.

21. The biasing circuit of claim 18 wherein said biasing transistor network comprises a plurality of field effect transistors, each one of said field effect transistors providing a bias current to a corresponding one of the multiple radio frequency power amplifier stages.

22. A method of biasing a first radio frequency power amplifier, said method comprising:

sensing a relative magnitude of a radio frequency signal to be amplified by the first radio frequency power amplifier;

generating a control current proportional to the relative magnitude of the radio frequency signal to be amplified;

mirroring the control current with a first desired current gain to produce a bias current proportional to said control current;

wherein said bias current is configured with the desired current gain based on a maximum expected signal amplitude of the radio frequency signal to be amplified, and wherein said bias current varies with the relative magnitude of the radio frequency signal to be amplified such that the first radio frequency power amplifier operates in a substantially linear mode across a range of relative magnitudes of the radio frequency signal to be amplified.

23. The method of claim 22 further comprising:

mirroring said control current with successively larger current gains scaled relative to said first current gain to produce a plurality of additional bias currents; and

biasing respective ones of a corresponding plurality of additional radio frequency power amplifiers successively arranged in an amplification signal path subsequent to said first radio frequency power amplifier with respective ones of said plurality of additional bias currents, such that each successive additional radio frequency power amplifier receives a proportionately larger bias current.

24. The method of claim 22 wherein said sensing a relative magnitude of a radio frequency signal to be amplified by the first radio frequency power amplifier comprises:

filtering the radio frequency signal to be amplified to produce a filtered signal;

rectifying the filtered signal to produce a DC signal; and

biasing a transistor control circuit with said DC signal such that said transistor control circuit produces a bias control current proportional to the relative magnitude of the radio frequency signal to be amplified.

25. The method of claim 22 wherein said mirroring the control current with a first desired current gain to produce a bias current proportional to said control current comprises configuring a field effect transistor to provide said bias current proportional to said bias control signal based on controlling a gate voltage of said field effect transistor with said bias control current.