Digital clock recovery loop

• US 6,285,261 B1
• Filed: 07/05/2000
• Issued: 09/04/2001
• Est. Priority Date: 08/29/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Griffin, Dan M., Pax, George E., OʼToole, James E.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/610,177
• Time in Patent Office: 426 Days
• Field of Search: 331/1.A, 331/4, 331/17, 331/25, 375/376, 375/374, 327/157, 327/159
• US Class Current: 331/17
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

Claims

1. A clock recovery method for extracting a clock signal from an input digital signal in a phase lock loop, the method comprising:

producing, with a voltage controlled oscillator having a control node, an output wave having a frequency that varies in response to a voltage applied to the control node;

controlling, with charge pump and loop filter circuitry, the rate of change of the voltage on the control node of the voltage controlled oscillator;

performing, with start-up circuitry, frequency discrimination and, in conjunction with the charge pump and loop filter circuitry, adjusting the voltage on the control node of the voltage controlled oscillator; and

performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator using a state machine.

2. A clock recovery method in accordance with claim 1 and further comprising applying, with bias circuitry, an offset voltage to the voltage controlled oscillator such that, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency of the voltage controlled oscillator when frequency lock is established.

3. A clock recovery method in accordance with claim 1 and further comprising making, with the state machine, finer adjustments to the voltage on the control node of the voltage controlled oscillator than the start-up circuit.

4. A clock recovery method in accordance with claim 1 and further comprising providing an input digital signal that comprises direct spread spectrum data.

5. A clock recovery method in accordance with claim 1 and further comprising implementing the state machine using digital circuitry.

6. A clock recovery method in accordance with claim 1 and further comprising providing an input digital signal that comprises direct spread spectrum data including a plurality of chips, and varying the output of the voltage controlled oscillator until a predetermined number of transitions of the output fit within a time interval of a predetermined number of chips in incoming data.

7. A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method comprising:

using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal;

extracting a clock from an input digital signal; and

performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

8. A method in accordance with claim 7 and further comprising making adjustments to the voltage on the control node, using the flip-flops, and wherein performing phase control and adjusting the voltage on the control node comprises making finer adjustments to the voltage on the control node of the voltage controlled oscillator than are made by the flip-flops.

9. A communications method for extracting a clock signal from incoming digital data using a clock recovery circuit configured as a phase lock loop, the method comprising:

producing an output wave using a voltage controlled oscillator having a control node and having an output at which the output wave is produced, wherein the output wave has a frequency that varies in response to a voltage applied to the control node;

controlling the rate of change of the voltage on the control node of the voltage controlled oscillator;

performing frequency discrimination and adjusting the voltage on the control node of the voltage controlled oscillator;

performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator; and

applying an offset voltage to the voltage controlled oscillator such that, in operation, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency lock frequency of the voltage controlled oscillator.

10. A clock recovery method for extracting a clock signal from an input digital signal in a phase lock loop, the method comprising:

producing, with a voltage controlled oscillator having a control node, an output wave having a frequency that varies in response to a voltage applied to the control node;

controlling, with charge pump and loop filter circuitry, the rate of change of the voltage on the control node of the voltage controlled oscillator;

performing, with start-up circuitry, frequency discrimination and, in conjunction with the charge pump and loop filter circuitry, adjusting the voltage on the control node of the voltage controlled oscillator; and

performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

11. A clock recovery method in accordance with claim 10 and further comprising applying an offset voltage to the voltage controlled oscillator such that, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency of the voltage controlled oscillator when frequency lock is established.