Nonvolatile ferroelectric memory

• US 6,285,576 B1
• Filed: 08/31/2000
• Issued: 09/04/2001
• Est. Priority Date: 09/08/1999
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/653,580
• Time in Patent Office: 369 Days
• Field of Search: 365/145, 365/149, 365/203
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

Nonvolatile ferroelectric memory stabilizes a reference level for obtaining a fast response speed and a reference level free from a noise. The nonvolatile memory device can include a cell array unit having at least one reference bitline, a plurality of main bitlines on one side of the reference bitline, and a plurality of pairs of first and second split wordlines in a direction crossing the bitlines. An equalizing unit equalizes adjacent bitlines inclusive of a reference bitline, among the main bitlines, and a precharge level adjustor adjusts a precharge level of the bitline in response to a combination of a first precharge control signal and a second precharge control signal. A sense amplifier unit is for sensing a signal on the main bitline, and a reference level generating unit is for receiving the reference bitline signal, and forwarding the reference bitline signal as a reference voltage for the sense amplifiers.

Claims

1. A nonvolatile ferroelectric memory, comprising:

a cell array having at least one reference bitline and a plurality of main bitlines that extend along a first direction, and a plurality of pairs of first and second split wordlines that extend along a second direction to cross the bitlines;

an equalizing unit that equalizes the main and reference bitlines;

a precharge level adjustor that adjusts a precharge level of the bitlines in response to a combination of a first precharge control signal and a second precharge control signal;

a sense amplifier that senses signals on the main bitlines; and

a reference level generator that receives a reference bitline signal and forwards a reference voltage for the sense amplifier.

2. The nonvolatile ferroelectric memory of claim 1, wherein the precharge level adjustor adjusts a voltage difference of the second precharge control signal from the first precharge control signal using the precharge level on the bitlines.

3. The nonvolatile ferroelectric memory of claim 1, wherein the precharge level adjustor includes a transistor having a first electrode coupled to a corresponding bitline, a second electrode that receives the second precharge control signal, and a control electrode that receives the first precharge control signal.

4. The nonvolatile ferroelectric memory of claim 3, wherein the corresponding bitline has a prescribed voltage being the first precharge control signal provided to the control electrode minus the second control signal provided to the second electrode.

5. The nonvolatile ferroelectric memory of claim 4, wherein the first precharge control signal has a level of 3Vtn, and the second precharge control signal has a level of Vtn, wherein the Vtn is a threshold voltage of an NMOS transistor.

6. The nonvolatile ferroelectric memory of claim 1, further comprising:

a precharge supply signal generator; and

a precharge control signal selecting and forwarding unit, wherein the first precharge control signal is generated at the precharge supply signal generator at a prescribed level, and provided to the precharge level adjustor through the precharge control signal selecting and forwarding unit.

7. The nonvolatile ferroelectric memory of claim 6, wherein the precharge supply signal generator comprises:

a transition generator that detects a pad signal to generate a transition detection signal;

an enable adjustor that receives the transition detection signal and provides a first enable signal and a second enable signal;

a reference signal forwarding unit enabled in response to the first enable signal to provide a precharge reference signal;

a precharge level comparator enabled in response to the second enable signal to compare the precharge reference signal to a feedback control signal;

a precharge level generator controlled by a driving signal from the precharge level comparator that outputs the feedback control signal; and

a first precharge control signal forwarding unit that receives a supply signal from the precharge level generator to provide the first precharge control signal.

8. The nonvolatile ferroelectric memory of claim 7, wherein the precharge level comparator compares a level of the precharge reference signal to a level of the feedback control signal to enable the precharge level generator to provide a higher output if the level of the feedback control signal is lower than the level of the reference signal.

9. The nonvolatile ferroelectric memory of claim 7, wherein the precharge level comparator unit disables the precharge level generator if a level of the feedback control signal is not less than a level of the precharge reference signal.

10. The nonvolatile ferroelectric memory of claim 7, wherein the transition generator comprises:

a pulse width adjusting and delay unit comprising,

a delay unit with an even number of invertors coupled in series to delay the pad signal for a prescribed time period, and

a plurality of MOS capacitors each coupled to an output terminal on alternate ones of the invertors to stabilize a corresponding output signal;

a pulse width generating unit having a first logic gate that logically processes outputs from a first invertor and a last invertor among the even number of invertors to adjust a width of an output signal; and

a driving unit having a plurality of logic gates that each invert an output signal of the pulse width generating unit.

11. The nonvolatile ferroelectric memory of claim 7, wherein the enable adjustor comprises:

an inverter that inverts the transition detection signal;

a first buffer unit that buffers a signal from the invertor; and

a first transistor that switches a first reference voltage in response to a signal from the first buffer unit.

12. The nonvolatile ferroelectric memory of claim 7, wherein the reference signal forwarding unit comprises:

a first transistor having a control electrode that receives a first enable signal from the enable adjustor and a second electrode coupled to a second reference voltage;

a second transistor having a second electrode coupled to the first transistor, a first electrode coupled to an output terminal, and a control electrode that receives the second reference voltage;

a third transistor having a control electrode that receives the first enable signal from the enable adjustor and a second electrode coupled to a first reference voltage;

a fourth transistor having a second electrode coupled to a first electrode of the third transistor, a first electrode coupled to the output terminal, and a control electrode coupled to the second reference voltage;

a fifth transistor coupled between the second reference voltage and the output terminal and having a control electrode that receives the first reference voltage;

sixth to ninth transistors coupled in series between the output terminal and the first reference voltage and each having control and first electrodes coupled together; and

an output voltage stabilizer that stabilizes a signal on the output terminal.

13. The nonvolatile ferroelectric memory of claim 12, wherein the voltage on the output terminal of the reference signal forwarding unit is determined by a ratio of a threshold voltage of the fifth transistor and the threshold voltages of the sixth, seventh, eighth, and ninth transistors.

14. The nonvolatile ferroelectric memory of claim 13, wherein the output terminal voltage of the reference signal forwarding unit has a level of 3Vtn, and wherein the fifth transistor is a PMOS transistor, and the other transistors are n-channel enhancement transistors.

15. A nonvolatile ferroelectric memory of claim 7, wherein the precharge level comparator compares a 3Vtn level of the precharge reference signal from the reference signal forwarding unit and a level of the feedback control signal from the precharge level generator to enable the precharge level generator according to a result of the comparison.

16. The nonvolatile ferroelectric memory of claim 7, wherein the precharge level comparator comprises:

a first transistor having a control electrode that receives a signal from the reference signal forwarding unit, and a second electrode that receives the second enable signal from the enable adjustor;

a second transistor having a control electrode that receives the feedback control signal from the precharge level generator, and a second electrode that receives the second enable signal;

a third transistor having a second electrode that receives a second reference voltage, a first electrode coupled to an output terminal and a first electrode of the first transistor to switch the second reference voltage in response to a control electrode voltage; and

a fourth transistor having a second electrode that receives the second reference voltage, a control and a first electrode coupled together, with the first electrode coupled to a first electrode of the second transistor.

17. The nonvolatile ferroelectric memory of claim 16, wherein the first and second transistors are n-channel enhancement transistors, and the third and fourth transistors are PMOS transistors.

18. The nonvolatile ferroelectric memory of claim 7, wherein the precharge level generator comprises:

a first inverter that inverts the driving signal from the precharge level comparator;

a second inverter that inverts an output signal from the first inverter;

a first transistor having a control electrode that receives the output signal from the first invertor, a second electrode coupled to a second reference voltage and a first electrode coupled to an input terminal on the first invertor; and

a second transistor controlled by a signal from the second invertor having a second electrode coupled to the second reference voltage and a first electrode coupled to a control electrode to provide the feedback control signal to the precharge level comparator and to an output terminal.

19. The nonvolatile ferroelectric memory of claim 7, wherein the first precharge control signal forwarding unit comprises:

a first transistor having a second electrode coupled to a second reference voltage and a first electrode coupled to an output terminal; and

four transistors coupled in series between the output terminal and a first reference voltage.

20. The nonvolatile ferroelectric memory of claim 19, wherein the first transistor is a PMOS transistor having a control electrode that receives the second reference voltage, and the four transistors coupled in series are n-channel enhancement transistors.

21. The nonvolatile ferroelectric memory of claim 6, wherein the precharge control signal selecting and forwarding unit comprises:

a first inverter that inverts the pad signal;

a first logic device that logically processes a signal from the first inverter and a cell block selection signal;

a second inverter that inverts a signal from the first logic device;

a first transistor having a second electrode that receives the first precharge control signal from the precharge supply signal generator and a first electrode coupled to an output terminal of the precharge control signal selecting and forwarding unit, and controlled by a signal from the first logic device;

a second transistor having a second electrode coupled to a first electrode of the first transistor, a first electrode coupled to a second reference voltage, and a control electrode that receives a signal from the second invertor;

a second logic device that logically processes a cell block selection signal and the transition detection signal; and

a third inverter that inverts an output signal from the second logic device.

22. The nonvolatile ferroelectric memory of claim 21, wherein the first precharge control signal is provided to the precharge level adjustor in a relevant cell block through the output terminal of the precharge control signal selecting and forwarding unit.

23. The nonvolatile ferroelectric memory of claim 1, wherein the reference level generator comprises:

a first comparing and amplifying unit that compares the reference bitline signal to a signal fed back thereto, and amplifies an output signal;

a second comparing and amplifying unit that compares the reference bitline signal to a signal fed back thereto, and amplifies an signal;

a reference output adjusting unit that adjusts a level of the reference signal in response to the output signals from the first and second comparing and amplifying units;

a reference output buffer that buffers the adjusted reference signal in the reference output adjusting unit; and

a reference output precharge adjusting unit that adjusts a precharge level of the reference bitline to a precharge level of a main bitline in response to the first precharge control signal and the transition detection signal.

24. The nonvolatile ferroelectric memory of claim 23, wherein the reference level generator comprises:

a first enable adjusting unit that enables the first comparing and amplifying unit; and

a second enable adjusting unit that enables the second comparing and amplifying units.

25. The nonvolatile ferroelectric memory of claim 23, wherein the first comparing and amplifying unit comprises:

a first transistor having a control electrode that receives a signal from the reference bitline, a second electrode coupled to the first enable adjusting unit, and a first electrode coupled to a first output terminal;

a second transistor having a second electrode coupled to a second reference voltage and a first electrode and a control electrode coupled together, with the first electrode coupled to the first output terminal;

a third transistor having a control electrode that receives the fed back signal, a second electrode coupled to the first enable adjusting unit, and a first electrode coupled to a second output terminal; and

a fourth transistor having a second electrode coupled to a second electrode of the second transistor, a first electrode coupled to the second output terminal, and a control electrode coupled to a control electrode of the second transistor.

26. The nonvolatile ferroelectric memory of claim 23, wherein reference output adjusting unit comprises:

a first transistor controlled by a signal from a second output terminal on the first comparing and amplifying unit and having a second electrode coupled to a fourth transistor in the first comparing and amplifying unit, and a first electrode coupled to a third transistor in the first comparing and amplifying unit;

a second transistor having a control electrode that receives a signal from a first output terminal on the second comparing and amplifying unit, a second electrode coupled to the second output terminal on the first comparing and amplifying unit, and a first electrode coupled to a first electrode of the first transistor;

a third transistor having a second electrode coupled to a second electrode of the first transistor, and a first electrode coupled to the third transistor in the first comparing and amplifying unit; and

a fourth transistor having a second electrode coupled to a first electrode of the third transistor and operative in response to a preset control signal.

27. A nonvolatile ferroelectric memory of claim 23, wherein the reference output buffer comprises:

a first transistor having a control electrode coupled to a first output terminal on the second comparing and amplifying unit, and a second electrode coupled to an output terminal on the reference output adjusting unit; and

a second transistor having a control electrode coupled to a second output terminal on the second comparing and amplifying unit and a second electrode coupled to a first electrode of the first transistor; and

a third transistor having a control electrode that receives a second reference voltage, a second electrode coupled to a second electrode of the first transistor, and a first electrode coupled to a first electrode of the second transistor.

28. The nonvolatile ferroelectric memory of claim 23, wherein the reference output precharge adjusting unit comprises:

a first transistor having a second electrode coupled to a second reference voltage and a control electrode that receives the first precharge control signal;

a second transistor having a second electrode coupled to a first electrode of the first transistor and a control electrode that receives an inverted preset control signal;

a third transistor having a second electrode coupled to a first electrode of the second transistor, and a control electrode that receives a transition detection signal, and a first electrode coupled to an output terminal; and

a fourth transistor having a second electrode coupled to a first reference voltage, a first electrode coupled to the output terminal, and a control electrode that receives an inverted transition detection signal.

29. A nonvolatile ferroelectric memory comprising:

a cell array unit having a first and second reference bitlines, and a plurality of main bitlines on one side of the reference bitlines that extend along a first direction, and a plurality of pairs of first and second split wordlines that extend in a second direction crossing the bitlines;

a first equalizer under the cell array unit that equalizes adjacent bitlines among odd numbered main bitlines and the first reference bitline;

a first precharge level adjustor that adjusts levels of the odd numbered bitlines and the first reference bitline in response to a first precharge control signal and a second precharge control signal;

a first sense amplifier that senses and amplifies signals on the odd numbered bitlines;

a first reference level generator that receives amplifies a signal on the first reference bitline and provides a result as a reference signal for the first sense amplifier;

a second equalizer over the cell array unit that equalizes adjacent bitlines among even numbered main bitlines and the second reference bitline;

a second precharge level adjustor that adjusts levels of the even numbered bitlines and the second reference bitline in response to the first precharge control signal and the second precharge control signal;

a second sense amplifier that senses and amplifies signals on the even numbered bitlines; and

a second reference level generator that amplifies a signal on the second reference bitline and provides a result as a reference signal to the second sense amplifier.

30. The nonvolatile ferroelectric memory of claim 29, wherein the first and second precharge level adjustors adjust a voltage difference of the second precharge control signal from the first precharge control signal to a precharge level on the bitlines.

31. The nonvolatile ferroelectric memory of claim 29, wherein each of the first and second precharge level adjustors includes transistors each having a first electrode coupled to a main bitline, a second electrode that receives the second precharge control signal, and a control electrode that receives the first precharge control signal.

32. The nonvolatile ferroelectric memory of claim 29, wherein the main bitline has a voltage provided thereto being the second precharge control signal provided to the second electrode subtracted from the first precharge control signal provided to the control electrode.

33. A memory device having a cell array with at least one reference bitline and a plurality of main bitlines that extend along a first direction, and a plurality of wordlines that extend along a second direction to cross the bitlines, a decoder coupled to the bitlines, a driving circuit coupled to the wordlines, and a sense amplifier that senses signals on the main bitlines, the improvement comprising:

a precharge level adjustor that adjusts a precharge level of the bitlines in response to a combination of the first precharge control signal and a second precharge control signal, wherein the precharge supply signal generator comprises,

a transition generator that detects a pad signal to generate a transition detection signal,

an enable adjustor that receives the transition detection signal and provides a first enable signal and a second enable signal,

a reference signal forwarding unit enabled in response to the first enable signal to provide a precharge reference signal,

a precharge level comparator enabled in response to the second enable signal to compare the precharge reference signal to a feedback control signal,

a precharge level generator controlled by a driving signal from the precharge level comparator that outputs the feedback control signal, and

a first precharge control signal forwarding unit that receives a supply signal from the precharge level generator to provide the first precharge control signal.

34. A memory device having a cell array with at least one reference bitline and a plurality of main bitlines that extend along a first direction, and a plurality of wordlines that extend along a second direction to cross the bitlines, a decoder coupled to the bitlines, a driving circuit coupled to the wordlines, and a sense amplifier that senses signals on the main bitlines, the improvement comprising:

a reference level generator that receives a reference bitline signal and forwards a reference voltage for the sense amplifiers, wherein the reference level generator comprises,

a first comparing and amplifying unit that compares the reference bitline signal to a signal fed back thereto, and amplifies an output signal,

a second comparing and amplifying unit that compares the reference bitline signal to a signal fed back thereto, and amplifies an signal,

a reference output adjusting unit that adjusts a level of the reference signal in response to the output signals from the first and second comparing and amplifying units,

a reference output buffer that buffers the adjusted reference signal in the reference output adjusting unit,

a reference output precharge adjusting unit that adjusts a precharge level of the reference bitline to a precharge level of a main bitline in response to a first precharge control signal and the transition detection signal,

a first enable adjusting unit that enables the first comparing and amplifying unit, and

a second enable adjusting unit that enables the second comparing and amplifying unit.